Searched refs:DG1_MSTR_UNIT_INTR (Results 1 – 3 of 3) sorted by relevance
2532 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0); in dg1_master_intr_disable_and_ack()2535 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR); in dg1_master_intr_disable_and_ack()2539 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val); in dg1_master_intr_disable_and_ack()2557 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ); in dg1_master_intr_enable()3512 POSTING_READ(DG1_MSTR_UNIT_INTR); in gen11_irq_postinstall()
502 I915_READ(DG1_MSTR_UNIT_INTR)); in i915_interrupt_info()
7757 #define DG1_MSTR_UNIT_INTR _MMIO(0x190008) macro