1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ 42 GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 43 #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ 44 (0x0000c018 + 0x1000 * (ee)) 45 46 #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ 47 GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 48 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ 49 (0x0000c01c + 0x1000 * (ee)) 50 51 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 52 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) 53 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ 54 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) 55 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 56 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 57 #define EE_FMASK GENMASK(7, 4) 58 #define CHID_FMASK GENMASK(12, 8) 59 /* The next field is present for GSI v2.0 and above */ 60 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 61 #define ERINDEX_FMASK GENMASK(18, 14) 62 #define CHSTATE_FMASK GENMASK(23, 20) 63 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 64 65 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 66 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) 67 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ 68 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) 69 #define R_LENGTH_FMASK GENMASK(15, 0) 70 71 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 72 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) 73 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ 74 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) 75 76 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 77 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) 78 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ 79 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) 80 81 #define GSI_CH_C_QOS_OFFSET(ch) \ 82 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) 83 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ 84 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) 85 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 86 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 87 #define USE_DB_ENG_FMASK GENMASK(9, 9) 88 /* The next field is present for GSI v2.0 and above */ 89 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 90 91 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 92 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) 93 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ 94 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) 95 96 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 97 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) 98 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ 99 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) 100 101 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 102 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) 103 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ 104 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) 105 106 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 107 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) 108 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ 109 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) 110 111 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 112 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) 113 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ 114 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) 115 #define EV_CHTYPE_FMASK GENMASK(3, 0) 116 #define EV_EE_FMASK GENMASK(7, 4) 117 #define EV_EVCHID_FMASK GENMASK(15, 8) 118 #define EV_INTYPE_FMASK GENMASK(16, 16) 119 #define EV_CHSTATE_FMASK GENMASK(23, 20) 120 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 121 122 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 123 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) 124 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ 125 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) 126 #define EV_R_LENGTH_FMASK GENMASK(15, 0) 127 128 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 129 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) 130 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ 131 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) 132 133 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 134 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) 135 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ 136 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) 137 138 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 139 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) 140 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ 141 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) 142 143 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 144 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) 145 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ 146 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) 147 #define MODT_FMASK GENMASK(15, 0) 148 #define MODC_FMASK GENMASK(23, 16) 149 #define MOD_CNT_FMASK GENMASK(31, 24) 150 151 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 152 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) 153 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ 154 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) 155 156 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 157 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) 158 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ 159 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) 160 161 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 162 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) 163 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ 164 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) 165 166 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 167 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) 168 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ 169 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) 170 171 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 172 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) 173 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ 174 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) 175 176 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 177 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) 178 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ 179 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) 180 181 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 182 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) 183 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ 184 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) 185 186 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 187 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) 188 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ 189 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) 190 191 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 192 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) 193 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ 194 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) 195 196 #define GSI_GSI_STATUS_OFFSET \ 197 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) 198 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ 199 (0x0001f000 + 0x4000 * (ee)) 200 #define ENABLED_FMASK GENMASK(0, 0) 201 202 #define GSI_CH_CMD_OFFSET \ 203 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) 204 #define GSI_EE_N_CH_CMD_OFFSET(ee) \ 205 (0x0001f008 + 0x4000 * (ee)) 206 #define CH_CHID_FMASK GENMASK(7, 0) 207 #define CH_OPCODE_FMASK GENMASK(31, 24) 208 209 #define GSI_EV_CH_CMD_OFFSET \ 210 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) 211 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ 212 (0x0001f010 + 0x4000 * (ee)) 213 #define EV_CHID_FMASK GENMASK(7, 0) 214 #define EV_OPCODE_FMASK GENMASK(31, 24) 215 216 #define GSI_GENERIC_CMD_OFFSET \ 217 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) 218 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ 219 (0x0001f018 + 0x4000 * (ee)) 220 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 221 #define GENERIC_CHID_FMASK GENMASK(9, 5) 222 #define GENERIC_EE_FMASK GENMASK(13, 10) 223 224 #define GSI_GSI_HW_PARAM_2_OFFSET \ 225 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) 226 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ 227 (0x0001f040 + 0x4000 * (ee)) 228 #define IRAM_SIZE_FMASK GENMASK(2, 0) 229 #define IRAM_SIZE_ONE_KB_FVAL 0 230 #define IRAM_SIZE_TWO_KB_FVAL 1 231 /* The next two values are available for GSI v2.0 and above */ 232 #define IRAM_SIZE_TWO_N_HALF_KB_FVAL 2 233 #define IRAM_SIZE_THREE_KB_FVAL 3 234 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 235 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 236 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 237 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 238 /* Fields below are present for GSI v2.0 and above */ 239 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 240 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 241 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 242 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 243 /* Fields below are present for GSI v2.2 and above */ 244 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 245 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 246 247 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 248 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) 249 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ 250 (0x0001f080 + 0x4000 * (ee)) 251 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 252 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) 253 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ 254 (0x0001f088 + 0x4000 * (ee)) 255 /* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */ 256 #define CH_CTRL_FMASK GENMASK(0, 0) 257 #define EV_CTRL_FMASK GENMASK(1, 1) 258 #define GLOB_EE_FMASK GENMASK(2, 2) 259 #define IEOB_FMASK GENMASK(3, 3) 260 #define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) 261 #define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) 262 #define GENERAL_FMASK GENMASK(6, 6) 263 #define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0) 264 265 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 266 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 267 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ 268 (0x0001f090 + 0x4000 * (ee)) 269 270 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 271 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 272 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ 273 (0x0001f094 + 0x4000 * (ee)) 274 275 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 276 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 277 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ 278 (0x0001f098 + 0x4000 * (ee)) 279 280 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 281 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 282 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ 283 (0x0001f09c + 0x4000 * (ee)) 284 285 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 286 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 287 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ 288 (0x0001f0a0 + 0x4000 * (ee)) 289 290 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 291 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 292 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 293 (0x0001f0a4 + 0x4000 * (ee)) 294 295 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 296 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) 297 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ 298 (0x0001f0b0 + 0x4000 * (ee)) 299 300 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 301 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) 302 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ 303 (0x0001f0b8 + 0x4000 * (ee)) 304 305 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 306 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) 307 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ 308 (0x0001f0c0 + 0x4000 * (ee)) 309 310 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 311 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) 312 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ 313 (0x0001f100 + 0x4000 * (ee)) 314 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 315 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) 316 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ 317 (0x0001f108 + 0x4000 * (ee)) 318 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 319 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) 320 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ 321 (0x0001f110 + 0x4000 * (ee)) 322 /* The masks below are used for the general IRQ STTS, EN, and CLR registers */ 323 #define ERROR_INT_FMASK GENMASK(0, 0) 324 #define GP_INT1_FMASK GENMASK(1, 1) 325 #define GP_INT2_FMASK GENMASK(2, 2) 326 #define GP_INT3_FMASK GENMASK(3, 3) 327 #define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0) 328 329 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 330 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) 331 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ 332 (0x0001f118 + 0x4000 * (ee)) 333 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 334 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) 335 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ 336 (0x0001f120 + 0x4000 * (ee)) 337 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 338 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) 339 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ 340 (0x0001f128 + 0x4000 * (ee)) 341 /* The masks below are used for the general IRQ STTS, EN, and CLR registers */ 342 #define BREAK_POINT_FMASK GENMASK(0, 0) 343 #define BUS_ERROR_FMASK GENMASK(1, 1) 344 #define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) 345 #define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) 346 #define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0) 347 348 #define GSI_CNTXT_INTSET_OFFSET \ 349 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) 350 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ 351 (0x0001f180 + 0x4000 * (ee)) 352 #define INTYPE_FMASK GENMASK(0, 0) 353 354 #define GSI_ERROR_LOG_OFFSET \ 355 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) 356 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ 357 (0x0001f200 + 0x4000 * (ee)) 358 #define ERR_ARG3_FMASK GENMASK(3, 0) 359 #define ERR_ARG2_FMASK GENMASK(7, 4) 360 #define ERR_ARG1_FMASK GENMASK(11, 8) 361 #define ERR_CODE_FMASK GENMASK(15, 12) 362 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 363 #define ERR_TYPE_FMASK GENMASK(27, 24) 364 #define ERR_EE_FMASK GENMASK(31, 28) 365 366 #define GSI_ERROR_LOG_CLR_OFFSET \ 367 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) 368 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ 369 (0x0001f210 + 0x4000 * (ee)) 370 371 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 372 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) 373 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ 374 (0x0001f400 + 0x4000 * (ee)) 375 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 376 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 377 #define GENERIC_EE_SUCCESS_FVAL 1 378 #define GENERIC_EE_INCORRECT_DIRECTION_FVAL 3 379 #define GENERIC_EE_INCORRECT_CHANNEL_FVAL 5 380 #define GENERIC_EE_NO_RESOURCES_FVAL 7 381 #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ 382 #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24) 383 384 #endif /* _GSI_REG_H_ */ 385