Searched refs:GICD_CTLR (Results 1 – 7 of 7) sorted by relevance
264 GicWaitForRwp(GICD_CTLR); in HalIrqMask()284 GicWaitForRwp(GICD_CTLR); in HalIrqUnmask()361 GIC_REG_32(GICD_CTLR) = 0; in HalIrqInit()362 GicWaitForRwp(GICD_CTLR); in HalIrqInit()384 GicWaitForRwp(GICD_CTLR); in HalIrqInit()392 GIC_REG_32(GICD_CTLR) = CTLR_ENALBE_G0 | CTLR_ENABLE_G1NS | CTLR_ARE_S; in HalIrqInit()
145 GIC_REG_32(GICD_CTLR) = 1; in HalIrqInit()
60 #define GICD_CTLR (GICD_OFFSET + 0x000) /* Distributor Control Regi… macro
71 case GICD_CTLR: in vgic_mmio_read_v3_misc()111 case GICD_CTLR: { in vgic_mmio_write_v3_misc()165 case GICD_CTLR: in vgic_mmio_uaccess_write_v3_misc()548 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
13 #define GICD_CTLR 0x0000 macro114 #define GICR_CTLR GICD_CTLR
107 + u32 gicd_ctlr = readl_relaxed(base + GICD_CTLR);116 writel_relaxed(0, base + GICD_CTLR);120 writel_relaxed(val, base + GICD_CTLR);
213 while (readl_relaxed(base + GICD_CTLR) & bit) { in gic_do_wait_for_rwp()778 writel_relaxed(0, base + GICD_CTLR); in gic_dist_init()815 writel_relaxed(val, base + GICD_CTLR); in gic_dist_init()971 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; in gic_dist_security_disabled()