Searched refs:IS_FPGA_MAXIMUS_DC (Results 1 – 25 of 28) sorted by relevance
12
69 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_translate_init()
71 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_factory_init()
112 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_clock()154 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_dispclk()
123 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce112_enable_display_power_gating()
135 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rv1_vbios_smu_set_dispclk()
421 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dp_set_dsc_on_rx()471 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()498 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
3189 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in core_link_enable_stream()3659 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment)); in dc_link_is_fec_supported()
141 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_hw_sequencer_construct()
141 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_hw_sequencer_construct()
448 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()479 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()
131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rn_vbios_smu_set_dispclk()
871 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in rn_clk_mgr_construct()925 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { in rn_clk_mgr_construct()
147 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn21_hw_sequencer_construct()
1499 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { in dcn21_pp_smu_create()1809 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dcn21_resource_construct()2090 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn21_resource_construct()
162 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce120_enable_display_power_gating()
72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ macro76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
513 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()525 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
479 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn20_clk_mgr_construct()
523 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn3_clk_mgr_construct()
888 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_reset_back_end_for_pipe()1279 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()1310 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()3072 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_prepare_bandwidth()3105 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_optimize_bandwidth()
1647 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn10_resource_construct()
892 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn21_dmcu_construct()
329 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()
925 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { in dce112_program_pix_clk()
208 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce110_enable_display_power_gating()