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Searched refs:IS_GEN9_LP (Results 1 – 25 of 31) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dvlv_dsi.c299 if (IS_GEN9_LP(dev_priv)) { in intel_dsi_compute_config()
524 else if (IS_GEN9_LP(dev_priv)) in intel_dsi_device_ready()
603 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? in vlv_dsi_clear_device_ready()
623 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && in vlv_dsi_clear_device_ready()
648 if (IS_GEN9_LP(dev_priv)) { in intel_dsi_port_enable()
668 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? in intel_dsi_port_enable()
705 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? in intel_dsi_port_disable()
783 if (IS_GEN9_LP(dev_priv)) { in intel_dsi_pre_enable()
934 if (IS_GEN9_LP(dev_priv)) { in intel_dsi_post_disable()
973 if (IS_GEN9_LP(dev_priv)) { in intel_dsi_post_disable()
[all …]
Dintel_gmbus.c101 else if (IS_GEN9_LP(dev_priv)) in get_gmbus_pin()
120 else if (IS_GEN9_LP(dev_priv)) in intel_gmbus_is_valid_pin()
592 if (IS_GEN9_LP(dev_priv)) in do_gmbus_xfer()
705 if (IS_GEN9_LP(dev_priv)) in do_gmbus_xfer()
Dintel_cdclk.c1608 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) in bxt_set_cdclk()
1709 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1774 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) in intel_cdclk_init_hw()
1789 if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915)) in intel_cdclk_uninit_hw()
1829 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) in intel_cdclk_can_cd2x_update()
2836 } else if (IS_GEN9_LP(dev_priv)) { in intel_init_cdclk_hooks()
2866 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)) in intel_init_cdclk_hooks()
Dintel_ddi.c1188 } else if (IS_GEN9_LP(dev_priv)) { in intel_ddi_hdmi_level()
2041 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { in intel_ddi_get_encoder_pipes()
2282 } else if (IS_GEN9_LP(dev_priv)) { in intel_ddi_dp_voltage_max()
3471 else if (IS_GEN9_LP(dev_priv)) in hsw_ddi_pre_enable_dp()
3545 else if (IS_GEN9_LP(dev_priv)) in intel_ddi_pre_enable_hdmi()
4117 else if (IS_GEN9_LP(dev_priv)) in intel_ddi_pre_pll_enable()
4462 if (IS_GEN9_LP(dev_priv)) in intel_ddi_get_config()
4535 if (IS_GEN9_LP(dev_priv)) in intel_ddi_compute_config()
4692 else if (IS_GEN9_LP(dev_priv)) in intel_ddi_init_dp_connector()
4932 if (IS_GEN9_LP(dev_priv)) in intel_ddi_a_force_4_lanes()
[all …]
Dintel_display_power.c712 if (IS_GEN(dev_priv, 9) && !IS_GEN9_LP(dev_priv) && in hsw_power_well_enabled()
812 else if (IS_GEN9_LP(dev_priv)) in gen9_dc_mask()
1192 if (IS_GEN9_LP(dev_priv)) in gen9_disable_dc_states()
4508 } else if (IS_GEN9_LP(dev_priv)) { in get_allowed_dc_mask()
5555 } else if (IS_GEN9_LP(i915)) { in intel_power_domains_init_hw()
5710 else if (IS_GEN9_LP(i915)) in intel_power_domains_suspend()
5832 if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) in intel_display_power_suspend_late()
5840 if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) { in intel_display_power_resume_early()
5853 } else if (IS_GEN9_LP(i915)) { in intel_display_power_suspend()
5874 } else if (IS_GEN9_LP(i915)) { in intel_display_power_resume()
Dintel_csr.c280 if (IS_GEN9_LP(dev_priv)) in gen9_set_dc_state_debugmask()
Dintel_dp_mst.c156 if (IS_GEN9_LP(dev_priv)) in intel_dp_mst_compute_config()
Dintel_dp.c329 } else if (IS_GEN9_LP(dev_priv)) { in intel_dp_set_source_rates()
1070 IS_GEN9_LP(dev_priv)))) in intel_power_sequencer_reset()
1092 if (IS_GEN9_LP(dev_priv)) in intel_power_sequencer_reset()
1115 if (IS_GEN9_LP(dev_priv)) in intel_pps_get_registers()
1126 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) in intel_pps_get_registers()
Dintel_hdmi.c2224 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) in hdmi_port_clock_valid()
3191 else if (IS_GEN9_LP(dev_priv)) in intel_hdmi_ddc_pin()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_sseu.c338 intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, in gen9_sseu_info_init()
339 IS_GEN9_LP(i915) ? 3 : 4, 8); in gen9_sseu_info_init()
409 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; in gen9_sseu_info_init()
411 IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1; in gen9_sseu_info_init()
414 if (IS_GEN9_LP(i915)) { in gen9_sseu_info_init()
Dintel_gt_clock_utils.c31 if (IS_GEN9_LP(gt->i915)) in read_clock_frequency()
Dintel_gtt.c255 else if (IS_GEN9_LP(i915)) in gtt_write_workarounds()
413 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) in setup_private_pat()
Ddebugfs_gt_pm.c311 if (IS_GEN9_LP(i915)) { in frequency_show()
436 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : in frequency_show()
449 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : in frequency_show()
Dintel_rc6.c476 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { in rc6_supported()
750 if (IS_GEN9_LP(i915)) { in intel_rc6_residency_ns()
Dintel_sseu_debugfs.c155 if (IS_GEN9_LP(gt->i915)) { in gen9_sseu_device_status()
Dintel_mocs.c339 } else if (IS_GEN9_LP(i915)) { in get_mocs_settings()
Dintel_workarounds.c433 if (IS_GEN9_LP(i915)) in gen9_ctx_workarounds_init()
1886 if (IS_GEN9_LP(i915)) in rcs_engine_wa_init()
Dintel_ggtt.c800 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) in ggtt_probe_common()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c28 if (IS_GEN9_LP(uncore->i915)) in guc_prepare_xfer()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Dintel_dram.c446 dram_info->is_16gb_dimm = !IS_GEN9_LP(i915); in intel_dram_detect()
451 if (IS_GEN9_LP(i915)) in intel_dram_detect()
Dintel_wopcm.c94 if (IS_GEN9_LP(i915)) in context_reserved_size()
Di915_irq.c170 else if (IS_GEN9_LP(dev_priv)) in intel_hpd_init_pins()
2285 if (IS_GEN9_LP(dev_priv)) { in gen8_de_irq_handler()
2299 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { in gen8_de_irq_handler()
3400 if (IS_GEN9_LP(dev_priv)) in gen8_de_irq_postinstall()
3407 if (IS_GEN9_LP(dev_priv)) in gen8_de_irq_postinstall()
3449 } else if (IS_GEN9_LP(dev_priv)) { in gen8_de_irq_postinstall()
4004 else if (IS_GEN9_LP(dev_priv)) in intel_irq_init()
Dintel_device_info.c217 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; in read_timestamp_frequency()
Di915_debugfs.c852 if (IS_GEN9_LP(dev_priv)) { in i915_frequency_info()
967 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : in i915_frequency_info()
980 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : in i915_frequency_info()
Di915_drv.h1613 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) macro

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