Searched refs:MIPI (Results 1 – 25 of 119) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soundwire/ |
| D | qcom,sdw.txt | 57 More info in MIPI Alliance SoundWire 1.0 Specifications.
64 More info in MIPI Alliance SoundWire 1.0 Specifications.
72 More info in MIPI Alliance SoundWire 1.0 Specifications.
78 More info in MIPI Alliance SoundWire 1.0 Specifications.
87 More info in MIPI Alliance SoundWire 1.0 Specifications.
95 More info in MIPI Alliance SoundWire 1.0 Specifications.
103 More info in MIPI Alliance SoundWire 1.0 Specifications.
112 More info in MIPI Alliance SoundWire 1.0 Specifications.
121 More info in MIPI Alliance SoundWire 1.0 Specifications.
131 More info in MIPI Alliance SoundWire 1.0 Specifications.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
20 MIPI CSI-2 clock is continuous or non-continuous.
25 For further information on the MIPI CSI-2 endpoint node properties, see
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| /kernel/linux/linux-5.10/drivers/media/platform/cadence/ |
| D | Kconfig | 14 tristate "Cadence MIPI-CSI2 RX Controller"
20 Support for the Cadence MIPI CSI2 Receiver controller.
26 tristate "Cadence MIPI-CSI2 TX Controller"
32 Support for the Cadence MIPI CSI2 Transceiver controller.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | samsung-mipi-csis.txt | 1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
15 - vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V);
42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
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| D | imx.txt | 27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
46 connecting with a MIPI CSI-2 source, and ports 1
49 MIPI CSI-2 virtual channel outputs.
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| D | imx7-mipi-csi2.txt | 7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
14 - interrupts : should contain MIPI CSIS interrupt;
25 provides power to MIPI CSIS core;
48 - data-lanes : (required) an array specifying active physical MIPI-CSI2
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| D | video-interfaces.txt | 467 1 - MIPI CSI-2 C-PHY
468 2 - MIPI CSI1
470 4 - MIPI CSI-2 D-PHY
491 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
496 serial busses only (e.g. MIPI CSI-2).
499 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
501 serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this
503 - clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous
505 - link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for
521 camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively.
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| /kernel/linux/linux-5.10/Documentation/driver-api/soundwire/ |
| D | summary.rst | 5 SoundWire is a new interface ratified in 2015 by the MIPI Alliance.
58 The MIPI SoundWire specification uses the term 'device' to refer to a Master
69 Programs all the MIPI-defined Slave registers. Represents a SoundWire
77 Driver controlling the Slave device. MIPI-specified registers are controlled
91 Bus implements API to read standard Master MIPI properties and also provides
133 MIPI specification, so Bus calls the "sdw_master_port_ops" callback
141 The MIPI specification requires each Slave interface to expose a unique
154 board-file, ACPI or DT. The MIPI Software specification defines additional
181 For capabilities, Bus implements API to read standard Slave MIPI properties
198 SoundWire MIPI specification 1.1 is available at:
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| /kernel/linux/linux-5.10/Documentation/admin-guide/media/ |
| D | imx7.rst | 16 - MIPI CSI-2 Receiver
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel
40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
55 can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO
76 On this platform an OV2680 MIPI CSI-2 module is connected to the internal MIPI
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| D | platform-cardlist.rst | 24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
46 rcar-csi2 R-Car MIPI CSI-2 Receiver
55 s5p-csis S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS)
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| D | imx.rst | 32 camera sensors over Parallel, BT.656/1120, and MIPI CSI-2 buses.
66 - MIPI CSI-2 Receiver for camera sensors with the MIPI CSI-2 bus
84 - Supports parallel, BT.565, and MIPI CSI-2 interfaces.
115 MIPI CSI-2 OV5640 sensor, requires the i.MX6 MIPI CSI-2 receiver. But
117 therefore does not require the MIPI CSI-2 receiver, so it is missing in
140 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive
141 the MIPI CSI-2 stream (usually from a MIPI CSI-2 camera sensor). It has
142 four source pads, corresponding to the four MIPI CSI-2 demuxed virtual
146 This entity actually consists of two sub-blocks. One is the MIPI CSI-2
147 core. This is a Synopsys Designware MIPI CSI-2 core. The other sub-block
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| D | fimc.rst | 28 - camera serial interface capture (MIPI-CSI2);
32 instance to any parallel video input or any MIPI-CSI front-end);
52 connections of the MIPI-CSIS device(s) to the FIMC entities.
85 MIPI-CSI receiver device (currently up to two).
129 sub-device node is created per each MIPI-CSIS device.
153 optional s5p-csis.ko (MIPI-CSI receiver subdev).
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
16 - phys: phandle link to the MIPI D-PHY controller.
22 MIPI TX Configuration Module
25 The MIPI TX configuration module controls the MIPI D-PHY.
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| /kernel/linux/linux-5.10/drivers/hwtracing/stm/ |
| D | Kconfig | 8 Trace Protocol (STP) format as defined by MIPI STP standards.
21 exclusively until the MIPI SyS-T support was added. Use this
24 The receiving side only needs to be able to decode the MIPI
31 tristate "MIPI SyS-T STM framing protocol driver"
34 This is an implementation of MIPI SyS-T protocol to be used
40 addition to the MIPI STP, in order to extract the data.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dsim.txt | 1 Exynos MIPI DSI Master
19 - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
20 - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
23 according to DSI host bindings (see MIPI DSI bindings [1])
32 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
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| /kernel/linux/linux-5.10/Documentation/trace/ |
| D | sys-t.rst | 4 MIPI SyS-T over STP
7 The MIPI SyS-T protocol driver can be used with STM class devices to
11 In order to use the MIPI SyS-T protocol driver with your STM device,
33 Now, with the MIPI SyS-T protocol driver, each policy node in the
52 MIPI SyS-T message header. It is off by default as the STP already
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | Kconfig | 13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
51 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
56 Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
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| /kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/ |
| D | Kconfig | 35 tristate "S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS) driver"
40 This is a V4L2 driver for Samsung S5P and EXYNOS4 SoC MIPI-CSI2
41 receiver (MIPI-CSIS) devices.
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| /kernel/linux/linux-5.10/drivers/gpu/drm/panel/ |
| D | Kconfig | 39 24 bit RGB per pixel. It provides a MIPI DSI interface to
79 KD35T133 controller for 320x480 LCD panels with MIPI-DSI
89 4-lane 800x1280 MIPI DSI panel.
92 tristate "Feiyang FY07024DI26A30-D MIPI-DSI LCD panel"
98 Feiyang FY07024DI26A30-D MIPI-DSI interface.
125 24 bit RGB per pixel. It provides a MIPI DSI interface to
147 24 bit RGB per pixel. It provides a MIPI DSI interface to
158 24 bit RGB per pixel. It provides a MIPI DSI interface to
169 24 bit RGB per pixel. It provides a MIPI DSI interface to
221 tristate "Mantix MLAF057WE51-X MIPI-DSI LCD panel"
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| /kernel/linux/linux-5.10/drivers/gpu/drm/stm/ |
| D | Kconfig | 19 tristate "STMicroelectronics specific extensions for Synopsys MIPI DSI"
23 Choose this option for MIPI DSI support on STMicroelectronics SoC.
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | configfs-stp-policy-p_sys-t | 8 tagged with this UUID in the MIPI SyS-T packet stream, to
17 Include payload length in the MIPI SyS-T header, boolean.
28 MIPI SyS-T packet metadata, if this many milliseconds have
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| /kernel/linux/linux-5.10/drivers/phy/amlogic/ |
| D | Kconfig | 59 Enable this to support the Meson MIPI + PCIE PHY found
64 tristate "Meson AXG MIPI + PCIE analog PHY driver"
70 Enable this to support the Meson MIPI + PCIE analog PHY
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| /kernel/linux/linux-5.10/drivers/media/platform/rcar-vin/ |
| D | Kconfig | 3 tristate "R-Car MIPI CSI-2 Receiver"
11 Support for Renesas R-Car MIPI CSI-2 receiver.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | mixel,mipi-dsi-phy.txt | 3 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
4 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
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| D | samsung-phy.txt | 1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
22 0 - MIPI CSIS 0,
23 1 - MIPI DSIM 0,
24 2 - MIPI CSIS 1,
25 3 - MIPI DSIM 1.
28 4 - MIPI CSIS 2.
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