Home
last modified time | relevance | path

Searched refs:MLX5_CAP_GEN (Results 1 – 25 of 76) sorted by relevance

1234

/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/
Dfw.c151 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { in mlx5_query_hca_caps()
157 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { in mlx5_query_hca_caps()
163 if (MLX5_CAP_GEN(dev, pg)) { in mlx5_query_hca_caps()
169 if (MLX5_CAP_GEN(dev, atomic)) { in mlx5_query_hca_caps()
175 if (MLX5_CAP_GEN(dev, roce)) { in mlx5_query_hca_caps()
181 if (MLX5_CAP_GEN(dev, nic_flow_table) || in mlx5_query_hca_caps()
182 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { in mlx5_query_hca_caps()
188 if (MLX5_CAP_GEN(dev, vport_group_manager) && in mlx5_query_hca_caps()
201 if (MLX5_CAP_GEN(dev, vector_calc)) { in mlx5_query_hca_caps()
207 if (MLX5_CAP_GEN(dev, qos)) { in mlx5_query_hca_caps()
[all …]
Dvport.c270 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list) : in mlx5_query_nic_vport_mac_list()
271 1 << MLX5_CAP_GEN(dev, log_max_current_mc_list); in mlx5_query_nic_vport_mac_list()
328 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list) : in mlx5_modify_nic_vport_mac_list()
329 1 << MLX5_CAP_GEN(dev, log_max_current_mc_list); in mlx5_modify_nic_vport_mac_list()
379 max_list_size = 1 << MLX5_CAP_GEN(dev, log_max_vlan_list); in mlx5_modify_nic_vport_vlans()
467 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) in mlx5_modify_nic_vport_node_guid()
527 is_group_manager = MLX5_CAP_GEN(dev, vport_group_manager); in mlx5_query_hca_vport_gid()
528 tbsz = mlx5_get_gid_table_len(MLX5_CAP_GEN(dev, gid_table_size)); in mlx5_query_hca_vport_gid()
561 if (MLX5_CAP_GEN(dev, num_ports) == 2) in mlx5_query_hca_vport_gid()
594 is_group_manager = MLX5_CAP_GEN(dev, vport_group_manager); in mlx5_query_hca_vport_pkey()
[all …]
Den_dcbnl.c60 #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
92 if (!MLX5_CAP_GEN(priv->mdev, dcbx)) in mlx5e_dcbnl_switch_to_host_mode()
117 if (!MLX5_CAP_GEN(priv->mdev, ets)) in mlx5e_dcbnl_ieee_getets()
326 if (!MLX5_CAP_GEN(priv->mdev, ets)) in mlx5e_dcbnl_ieee_setets()
422 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) { in mlx5e_dcbnl_setdcbx()
454 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) || in mlx5e_dcbnl_ieee_setapp()
507 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) || in mlx5e_dcbnl_ieee_delapp()
629 if (!MLX5_CAP_GEN(mdev, ets)) in mlx5e_dcbnl_setall()
738 if (!MLX5_CAP_GEN(priv->mdev, ets)) { in mlx5e_dcbnl_getpgtccfgtx()
1025 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) in mlx5e_dcbnl_build_netdev()
[all …]
Dmlx5_core.h208 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
209 MLX5_CAP_GEN((mdev), pps_modify) && \
233 return MLX5_CAP_GEN(dev, vport_group_manager) && in mlx5_lag_is_lacp_owner()
234 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) && in mlx5_lag_is_lacp_owner()
235 MLX5_CAP_GEN(dev, lag_master); in mlx5_lag_is_lacp_owner()
Duar.c65 if (MLX5_CAP_GEN(mdev, uar_4k)) in uars_per_sys_page()
66 return MLX5_CAP_GEN(mdev, num_of_uars_per_page); in uars_per_sys_page()
75 if (MLX5_CAP_GEN(mdev, uar_4k)) in uar2pfn()
201 (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) + MLX5_BF_OFFSET; in map_offset()
281 bf_reg_size = 1 << MLX5_CAP_GEN(dev, log_bf_reg_size); in addr_to_dbi_in_syspage()
Deq.c319 if (!param->mask[0] && MLX5_CAP_GEN(dev, log_max_uctx)) in create_map_eq()
566 if (MLX5_CAP_GEN(dev, general_notification_event)) in gather_async_events_mask()
569 if (MLX5_CAP_GEN(dev, port_module_event)) in gather_async_events_mask()
577 if (MLX5_CAP_GEN(dev, fpga)) in gather_async_events_mask()
583 if (MLX5_CAP_GEN(dev, temp_warn_event)) in gather_async_events_mask()
589 if (MLX5_CAP_GEN(dev, max_num_of_monitor_counters)) in gather_async_events_mask()
598 if (MLX5_CAP_GEN(dev, event_cap)) in gather_async_events_mask()
950 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? in mlx5_eq_table_create()
951 MLX5_CAP_GEN(dev, max_num_eqs) : in mlx5_eq_table_create()
952 1 << MLX5_CAP_GEN(dev, log_max_eq); in mlx5_eq_table_create()
Dpci_irq.c265 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? in mlx5_irq_table_create()
266 MLX5_CAP_GEN(dev, max_num_eqs) : in mlx5_irq_table_create()
267 1 << MLX5_CAP_GEN(dev, log_max_eq); in mlx5_irq_table_create()
271 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + in mlx5_irq_table_create()
Den_ethtool.c497 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) in mlx5e_ethtool_get_coalesce()
567 if (!MLX5_CAP_GEN(mdev, cq_moderation)) in mlx5e_ethtool_set_coalesce()
1410 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) in mlx5e_ethtool_set_pauseparam()
1442 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || in mlx5e_ethtool_get_ts_info()
1471 if (MLX5_CAP_GEN(mdev, wol_g)) in mlx5e_get_wol_supported()
1474 if (MLX5_CAP_GEN(mdev, wol_s)) in mlx5e_get_wol_supported()
1477 if (MLX5_CAP_GEN(mdev, wol_a)) in mlx5e_get_wol_supported()
1480 if (MLX5_CAP_GEN(mdev, wol_b)) in mlx5e_get_wol_supported()
1483 if (MLX5_CAP_GEN(mdev, wol_m)) in mlx5e_get_wol_supported()
1486 if (MLX5_CAP_GEN(mdev, wol_u)) in mlx5e_get_wol_supported()
[all …]
Den_common.c66 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); in mlx5e_mkey_set_relaxed_ordering()
67 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); in mlx5e_mkey_set_relaxed_ordering()
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/en/
Dmonitor_stats.c27 if (!MLX5_CAP_GEN(mdev, max_num_of_monitor_counters)) in mlx5e_monitor_counter_supported()
30 MLX5_CAP_GEN(mdev, num_ppcnt_monitor_counters) < in mlx5e_monitor_counter_supported()
33 if (MLX5_CAP_GEN(mdev, num_q_monitor_counters) < in mlx5e_monitor_counter_supported()
103 int max_num_of_counters = MLX5_CAP_GEN(mdev, max_num_of_monitor_counters); in mlx5e_set_monitor_counter()
104 int num_q_counters = MLX5_CAP_GEN(mdev, num_q_monitor_counters); in mlx5e_set_monitor_counter()
106 MLX5_CAP_GEN(mdev, num_ppcnt_monitor_counters); in mlx5e_set_monitor_counter()
Dport_buffer.h41 #define MLX5_BUFFER_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, pcam_reg) && \
Dtc_tun_geneve.c12 return !!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) & MLX5_FLEX_PROTO_GENEVE); in mlx5e_tc_tun_can_offload_geneve()
159 u8 max_tlv_option_data_len = MLX5_CAP_GEN(priv->mdev, max_geneve_tlv_option_data_len); in mlx5e_tc_tun_parse_geneve_options()
160 u8 max_tlv_options = MLX5_CAP_GEN(priv->mdev, max_geneve_tlv_options); in mlx5e_tc_tun_parse_geneve_options()
/kernel/linux/linux-5.10/drivers/infiniband/hw/mlx5/
Dmain.c111 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); in mlx5_ib_port_link_layer()
502 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); in mlx5_query_port_roce()
610 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) in mlx5_use_mad_ifc()
611 return !MLX5_CAP_GEN(dev->mdev, ib_virt); in mlx5_use_mad_ifc()
707 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, in mlx5_query_max_pkeys()
791 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); in mlx5_ib_query_device()
828 if (MLX5_CAP_GEN(mdev, pkv)) in mlx5_ib_query_device()
830 if (MLX5_CAP_GEN(mdev, qkv)) in mlx5_ib_query_device()
832 if (MLX5_CAP_GEN(mdev, apm)) in mlx5_ib_query_device()
834 if (MLX5_CAP_GEN(mdev, xrc)) in mlx5_ib_query_device()
[all …]
Dcounters.c272 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { in mlx5_ib_get_hw_stats()
387 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { in mlx5_ib_fill_counters()
394 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { in mlx5_ib_fill_counters()
401 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { in mlx5_ib_fill_counters()
408 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) { in mlx5_ib_fill_counters()
415 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { in mlx5_ib_fill_counters()
438 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) in __mlx5_ib_alloc_counters()
441 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) in __mlx5_ib_alloc_counters()
444 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) in __mlx5_ib_alloc_counters()
447 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) in __mlx5_ib_alloc_counters()
[all …]
Dqp.c358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) in set_rq_size()
393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { in set_rq_size()
396 MLX5_CAP_GEN(dev->mdev, in set_rq_size()
523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { in calc_sq_size()
525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); in calc_sq_size()
535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { in calc_sq_size()
539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); in calc_sq_size()
562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { in set_user_buf_size()
564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); in set_user_buf_size()
576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { in set_user_buf_size()
[all …]
Dmlx5_ib.h1449 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? in get_uars_per_sys_page()
1477 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) in mlx5_ib_can_load_pas_with_umr()
1484 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && in mlx5_ib_can_load_pas_with_umr()
1502 MLX5_CAP_GEN(dev->mdev, atomic) && in mlx5_ib_can_reconfig_with_umr()
1503 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) in mlx5_ib_can_reconfig_with_umr()
1507 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && in mlx5_ib_can_reconfig_with_umr()
1508 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) in mlx5_ib_can_reconfig_with_umr()
1512 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) && in mlx5_ib_can_reconfig_with_umr()
1513 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) in mlx5_ib_can_reconfig_with_umr()
1524 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && in mlx5_ib_lag_should_assign_affinity()
[all …]
Dcq.c697 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) in mini_cqe_res_format_to_hw()
782 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) || in create_cq_user()
784 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) { in create_cq_user()
807 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) { in create_cq_user()
937 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) in mlx5_ib_create_cq()
944 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) in mlx5_ib_create_cq()
1113 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) in mlx5_ib_modify_cq()
1255 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { in mlx5_ib_resize_cq()
1261 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { in mlx5_ib_resize_cq()
1264 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); in mlx5_ib_resize_cq()
[all …]
Dsrq.c116 if (MLX5_CAP_GEN(dev->mdev, cqe_version) == MLX5_CQE_VERSION_V1 && in create_srq_user()
180 if (MLX5_CAP_GEN(dev->mdev, cqe_version) == MLX5_CQE_VERSION_V1 && in create_srq_kernel()
227 __u32 max_srq_wqes = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); in mlx5_ib_create_srq()
286 MLX5_CAP_GEN(dev->mdev, log_tag_matching_list_sz)) { in mlx5_ib_create_srq()
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Degress_ofld.c54 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) { in esw_acl_egress_ofld_rules_create()
101 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) { in esw_acl_egress_ofld_groups_create()
162 !MLX5_CAP_GEN(esw->dev, prio_tag_required)) in esw_acl_egress_ofld_setup()
172 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) in esw_acl_egress_ofld_setup()
228 fwd_dest.vport.vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id); in mlx5_esw_acl_egress_vport_bond()
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/accel/
Dipsec_offload.h15 if (!MLX5_CAP_GEN(mdev, ipsec_offload)) in mlx5_is_ipsec_device()
18 if (!MLX5_CAP_GEN(mdev, log_max_dek)) in mlx5_is_ipsec_device()
Dtls.h48 return MLX5_CAP_GEN(mdev, tls_tx); in mlx5_accel_is_ktls_tx()
53 return MLX5_CAP_GEN(mdev, tls_rx); in mlx5_accel_is_ktls_rx()
62 if (!MLX5_CAP_GEN(mdev, log_max_dek)) in mlx5_accel_is_ktls_device()
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_cmd.c91 caps->prio_tag_required = MLX5_CAP_GEN(mdev, prio_tag_required); in mlx5dr_cmd_query_device()
92 caps->eswitch_manager = MLX5_CAP_GEN(mdev, eswitch_manager); in mlx5dr_cmd_query_device()
93 caps->gvmi = MLX5_CAP_GEN(mdev, vhca_id); in mlx5dr_cmd_query_device()
94 caps->flex_protocols = MLX5_CAP_GEN(mdev, flex_parser_protocols); in mlx5dr_cmd_query_device()
95 caps->sw_format_ver = MLX5_CAP_GEN(mdev, steering_format_version); in mlx5dr_cmd_query_device()
98 caps->flex_parser_id_icmp_dw0 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw0); in mlx5dr_cmd_query_device()
99 caps->flex_parser_id_icmp_dw1 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw1); in mlx5dr_cmd_query_device()
104 MLX5_CAP_GEN(mdev, flex_parser_id_icmpv6_dw0); in mlx5dr_cmd_query_device()
106 MLX5_CAP_GEN(mdev, flex_parser_id_icmpv6_dw1); in mlx5dr_cmd_query_device()
Dmlx5dr.h127 return MLX5_CAP_GEN(dev, roce) && in mlx5dr_is_supported()
130 (MLX5_CAP_GEN(dev, steering_format_version) <= in mlx5dr_is_supported()
/kernel/linux/linux-5.10/include/linux/mlx5/
Dvport.h48 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
49 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dgid.c135 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_core_roce_gid_set()
150 if (MLX5_CAP_GEN(dev, num_vhca_ports) > 0) in mlx5_core_roce_gid_set()

1234