| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/ |
| D | pvpanic-mmio.txt | 1 * QEMU PVPANIC MMIO Configuration bindings
4 MMIO Configuration interface on the "virt" machine.
14 - reg: the MMIO region used by the device.
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| /kernel/linux/linux-5.10/Documentation/admin-guide/hw-vuln/ |
| D | processor_mmio_stale_data.rst | 2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
8 vulnerabilities require the attacker to have access to MMIO, many environments
9 are not affected. System environments using virtualization where MMIO access is
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
49 processors, MMIO primary reads will return 64 bytes of data to the core fill
57 Some endpoint MMIO registers incorrectly handle writes that are smaller than
117 specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
145 is more critical, or the untrusted software has no MMIO access). Note that
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/security/tpm/ |
| D | tpm_tis_mmio.txt | 1 Trusted Computing Group MMIO Trusted Platform Module
4 is the standard protocol defined to access the TPM via MMIO. Typically
15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
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| /kernel/linux/linux-5.10/Documentation/userspace-api/accelerators/ |
| D | ocxl.rst | 66 work with, the size of its MMIO areas, ...
70 MMIO chapter
73 OpenCAPI defines two MMIO areas for each AFU:
75 * the global MMIO area, with registers pertinent to the whole AFU.
76 * a per-process MMIO area, which has a fixed size for each context.
158 MMIO areas, the AFU version, and the PASID for the current context.
175 A process can mmap the per-process MMIO area for interactions with the
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/ |
| D | common.c | 1120 #define MMIO BIT(1) macro
1131 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1132 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1134 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1136 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED),
1137 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED),
1138 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED),
1139 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED),
1140 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED),
1142 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
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| /kernel/linux/linux-5.10/Documentation/ia64/ |
| D | aliasing.rst | 49 address space because some machines omit some or all of the MMIO
54 This contains only system memory; it does not contain MMIO space.
108 Since the EFI memory map does not describe MMIO on some
115 only allows mmap of the one megabyte "legacy MMIO" area for a
129 This is an MMIO mmap of PCI functions, which additionally may or
147 but could be accessed this way. For example, registers in MMIO
175 mmap of various MMIO regions from /dev/mem by "X" on Intel platforms
178 The EFI memory map may not report these MMIO regions.
226 0x00000-0xFFFFF WB only (no VGA MMIO hole)
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| /kernel/linux/linux-5.10/drivers/net/fddi/ |
| D | Kconfig | 43 prompt "Use MMIO instead of IOP" if PCI || EISA
49 (MMIO) as appropriate instead of programmed I/O ports (IOP).
53 Conversely some PCIe host bridges do not support IOP, so MMIO
56 of I/O ports, so MMIO is always used for these (DEFTA) adapters.
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | TODO | 55 driver infrastructure for doing simpler MMIO GPIO devices and there was
62 - Get rid of struct of_mm_gpio_chip altogether: use the generic MMIO
107 Generic MMIO GPIO
109 The GPIO drivers can utilize the generic MMIO helper library in many
110 cases, and the helper library should be as helpful as possible for MMIO
116 dry-code conversions to MMIO GPIO for maintainers to test
118 - Expand the MMIO GPIO or write a new library for regmap-based I/O
122 - Expand the MMIO GPIO or write a new library for port-mapped I/O
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regmap/ |
| D | regmap.txt | 10 Regmap defaults to little-endian register access on MMIO based
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
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| /kernel/linux/linux-5.10/Documentation/powerpc/ |
| D | cxl.rst | 99 MMIO space
102 A portion of the accelerator MMIO space can be directly mapped
141 context. Master contexts have access to the full MMIO space an
143 MMIO space an AFU provides.
147 /dev/cxl/afu0.0d. This will have access to the entire MMIO space
251 An AFU may have an MMIO space to facilitate communication with the
252 AFU. If it does, the MMIO space can be accessed via mmap. The size
257 the MMIO space and slave contexts are allowed to only map the per
258 process MMIO space associated with the context. In dedicated
259 process mode the entire MMIO space can always be mapped.
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| D | pci_iov_resource_on_powernv.rst | 13 This document describes the requirement from hardware for PCI MMIO resource
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
96 maps each segment to a PE#. That allows portions of the MMIO space
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
222 The IODA2 platform has 16 M64 windows, which are used to map MMIO
223 range to PE#. Each M64 window defines one MMIO range and this range is
232 device's MMIO range.
236 segments [total_VFs, 255] of the M64 window may map to some MMIO range on
287 In IODA2, the MMIO address determines the PE#. If the address is in an M32
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| /kernel/linux/linux-5.10/drivers/soc/aspeed/ |
| D | Kconfig | 26 tristate "Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC bridge control"
28 Control Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC mappings through
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| /kernel/linux/linux-5.10/Documentation/PCI/ |
| D | pci.rst | 46 - Request MMIO/IOP resources
62 - Release MMIO/IOP resources
182 - Request MMIO/IOP resources
235 Request MMIO/IOP resources
237 Memory (MMIO), and I/O port addresses should NOT be read directly
253 determine MMIO and IO Port resource availability _after_ calling
257 (for MMIO ranges) and request_region() (for IO Port ranges).
353 This guarantee allows the driver to omit MMIO reads to flush
371 - Disable device from responding to MMIO/IO Port addresses
372 - Release MMIO/IO Port resource(s)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | ti,am654-hbmc.txt | 8 MMIO access to attached flash devices
9 - ranges : Address translation from offset within CS to allocated MMIO
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| /kernel/linux/linux-5.10/Documentation/mhi/ |
| D | mhi.rst | 25 MMIO section in MHI Internals
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
30 Following are the major components of MMIO register space:
160 to access device MMIO register space.
165 programming MMIO registers.
192 the device's MMIO register space. To initialize the MHI in a device,
198 * Programs MHI MMIO registers and sets device into MHI_M0 state.
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| /kernel/linux/linux-5.10/Documentation/translations/ko_KR/ |
| D | memory-barriers.txt | 121 - 캐시 일관성 vs MMIO.
1822 합니다. 하지만, 느슨한 순서 규칙의 메모리 I/O 윈도우를 통한 MMIO 의 효과를
1898 쓰기가 MMIO 영역에의 쓰기 전에 완료되었을 것을 보장하므로 writel() 앞에
2494 readX() 와 writeX() MMIO 액세스 함수는 접근되는 주변장치로의 포인터를
2499 순서지어집니다. 이는 같은 CPU 쓰레드에 의한 특정 디바이스로의 MMIO
2505 호출된 MMIO 레지스터 쓰기는 해당 락의 획득에 일관적인 순서로 도달할
2512 전송을 시작시키기 위해 MMIO 컨트롤 레지스터에 쓰기를 할 때 DMA
2518 읽기는 이 DMA 수신의 완료를 표시하는 DMA 엔진의 MMIO 상태 레지스터
2523 주변장치로의 두개의 MMIO 레지스터 쓰기가 행해지는데 첫번째 쓰기가
2547 readsX() 와 writesX() MMIO 액세스 함수는 DMA 를 수행하는데 적절치 않은,
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| /kernel/linux/linux-5.10/Documentation/trace/ |
| D | mmiotrace.rst | 10 MMIO tracing was originally developed by Intel around 2003 for their Fault
12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
67 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
182 - replaying MMIO logs, i.e., re-executing the recorded writes
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| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | overview.rst | 121 A DPRC has a mappable MMIO region (an MC portal) that can be used
172 supports and a summary of key resources of the object (MMIO regions
180 - MMIO regions: none
190 - MMIO regions: none
200 from the queues themselves. The DPIO provides an MMIO interface to
202 to the DPIO MMIO region, which includes the target queue number.
207 - MMIO regions: queue operations, buffer management
216 - MMIO regions: none
226 - MMIO regions: MC command portal
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| /kernel/linux/linux-5.10/drivers/mux/ |
| D | Kconfig | 49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/dlink/ |
| D | Kconfig | 46 bool "Use MMIO instead of PIO"
50 Do NOT enable this by default, PIO (enabled when MMIO is disabled)
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| /kernel/linux/linux-5.10/drivers/net/ethernet/via/ |
| D | Kconfig | 36 bool "Use MMIO instead of PIO"
39 This instructs the driver to use PCI shared memory (MMIO) instead of
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| /kernel/linux/linux-5.10/Documentation/virt/kvm/ |
| D | mmu.rst | 312 accessing MMIO and cached MMIO information is available.
316 MMIO sptes" below)
439 Fast invalidation of MMIO sptes
442 As mentioned in "Reaction to events" above, kvm will cache MMIO
448 MMIO sptes have a few spare bits, which are used to store a
453 When KVM finds an MMIO spte, it checks the generation number of the spte.
455 number, it will ignore the cached MMIO information and handle the page
463 stored into the MMIO spte. Thus, the MMIO spte might be created based on
469 want to use an MMIO sptes created with an odd generation number, and we can do
470 this without losing a bit in the MMIO spte. The "update in-progress" bit of the
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 5 write to an MMIO address.
14 - The doorbell (the MMIO address written to).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 15 - ranges: ranges describing the MMIO registers to control the PCIe
21 The ranges describing the MMIO registers have the following layout:
27 * r is a 32-bits value that gives the offset of the MMIO
31 * s is a 32-bits value that give the size of this MMIO
62 - assigned-addresses: reference to the MMIO registers used to control
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | amazon,al-thermal.txt | 3 Simple thermal device that allows temperature reading by a single MMIO
|