1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 MediaTek Inc. 4 */ 5 6 #ifndef __MT6360_H__ 7 #define __MT6360_H__ 8 9 #include <linux/regmap.h> 10 11 enum { 12 MT6360_SLAVE_PMU = 0, 13 MT6360_SLAVE_PMIC, 14 MT6360_SLAVE_LDO, 15 MT6360_SLAVE_TCPC, 16 MT6360_SLAVE_MAX, 17 }; 18 19 #define MT6360_PMU_SLAVEID (0x34) 20 #define MT6360_PMIC_SLAVEID (0x1A) 21 #define MT6360_LDO_SLAVEID (0x64) 22 #define MT6360_TCPC_SLAVEID (0x4E) 23 24 struct mt6360_pmu_data { 25 struct i2c_client *i2c[MT6360_SLAVE_MAX]; 26 struct device *dev; 27 struct regmap *regmap; 28 struct regmap_irq_chip_data *irq_data; 29 unsigned int chip_rev; 30 }; 31 32 /* PMU register defininition */ 33 #define MT6360_PMU_DEV_INFO (0x00) 34 #define MT6360_PMU_CORE_CTRL1 (0x01) 35 #define MT6360_PMU_RST1 (0x02) 36 #define MT6360_PMU_CRCEN (0x03) 37 #define MT6360_PMU_RST_PAS_CODE1 (0x04) 38 #define MT6360_PMU_RST_PAS_CODE2 (0x05) 39 #define MT6360_PMU_CORE_CTRL2 (0x06) 40 #define MT6360_PMU_TM_PAS_CODE1 (0x07) 41 #define MT6360_PMU_TM_PAS_CODE2 (0x08) 42 #define MT6360_PMU_TM_PAS_CODE3 (0x09) 43 #define MT6360_PMU_TM_PAS_CODE4 (0x0A) 44 #define MT6360_PMU_IRQ_IND (0x0B) 45 #define MT6360_PMU_IRQ_MASK (0x0C) 46 #define MT6360_PMU_IRQ_SET (0x0D) 47 #define MT6360_PMU_SHDN_CTRL (0x0E) 48 #define MT6360_PMU_TM_INF (0x0F) 49 #define MT6360_PMU_I2C_CTRL (0x10) 50 #define MT6360_PMU_CHG_CTRL1 (0x11) 51 #define MT6360_PMU_CHG_CTRL2 (0x12) 52 #define MT6360_PMU_CHG_CTRL3 (0x13) 53 #define MT6360_PMU_CHG_CTRL4 (0x14) 54 #define MT6360_PMU_CHG_CTRL5 (0x15) 55 #define MT6360_PMU_CHG_CTRL6 (0x16) 56 #define MT6360_PMU_CHG_CTRL7 (0x17) 57 #define MT6360_PMU_CHG_CTRL8 (0x18) 58 #define MT6360_PMU_CHG_CTRL9 (0x19) 59 #define MT6360_PMU_CHG_CTRL10 (0x1A) 60 #define MT6360_PMU_CHG_CTRL11 (0x1B) 61 #define MT6360_PMU_CHG_CTRL12 (0x1C) 62 #define MT6360_PMU_CHG_CTRL13 (0x1D) 63 #define MT6360_PMU_CHG_CTRL14 (0x1E) 64 #define MT6360_PMU_CHG_CTRL15 (0x1F) 65 #define MT6360_PMU_CHG_CTRL16 (0x20) 66 #define MT6360_PMU_CHG_AICC_RESULT (0x21) 67 #define MT6360_PMU_DEVICE_TYPE (0x22) 68 #define MT6360_PMU_QC_CONTROL1 (0x23) 69 #define MT6360_PMU_QC_CONTROL2 (0x24) 70 #define MT6360_PMU_QC30_CONTROL1 (0x25) 71 #define MT6360_PMU_QC30_CONTROL2 (0x26) 72 #define MT6360_PMU_USB_STATUS1 (0x27) 73 #define MT6360_PMU_QC_STATUS1 (0x28) 74 #define MT6360_PMU_QC_STATUS2 (0x29) 75 #define MT6360_PMU_CHG_PUMP (0x2A) 76 #define MT6360_PMU_CHG_CTRL17 (0x2B) 77 #define MT6360_PMU_CHG_CTRL18 (0x2C) 78 #define MT6360_PMU_CHRDET_CTRL1 (0x2D) 79 #define MT6360_PMU_CHRDET_CTRL2 (0x2E) 80 #define MT6360_PMU_DPDN_CTRL (0x2F) 81 #define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) 82 #define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) 83 #define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) 84 #define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) 85 #define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) 86 #define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) 87 #define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) 88 #define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) 89 #define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) 90 #define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) 91 #define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) 92 #define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) 93 #define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) 94 #define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) 95 #define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) 96 #define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) 97 #define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) 98 #define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) 99 #define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) 100 #define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) 101 #define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) 102 #define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) 103 #define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) 104 #define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) 105 #define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) 106 #define MT6360_PMU_BC12_CTRL (0x49) 107 #define MT6360_PMU_CHG_STAT (0x4A) 108 #define MT6360_PMU_RESV1 (0x4B) 109 #define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) 110 #define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) 111 #define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) 112 #define MT6360_PMU_TYPEC_OTP_CTRL (0x51) 113 #define MT6360_PMU_ADC_BAT_DATA_H (0x52) 114 #define MT6360_PMU_ADC_BAT_DATA_L (0x53) 115 #define MT6360_PMU_IMID_BACKBST_ON (0x54) 116 #define MT6360_PMU_IMID_BACKBST_OFF (0x55) 117 #define MT6360_PMU_ADC_CONFIG (0x56) 118 #define MT6360_PMU_ADC_EN2 (0x57) 119 #define MT6360_PMU_ADC_IDLE_T (0x58) 120 #define MT6360_PMU_ADC_RPT_1 (0x5A) 121 #define MT6360_PMU_ADC_RPT_2 (0x5B) 122 #define MT6360_PMU_ADC_RPT_3 (0x5C) 123 #define MT6360_PMU_ADC_RPT_ORG1 (0x5D) 124 #define MT6360_PMU_ADC_RPT_ORG2 (0x5E) 125 #define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) 126 #define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) 127 #define MT6360_PMU_CHG_CTRL19 (0x61) 128 #define MT6360_PMU_VDDASUPPLY (0x62) 129 #define MT6360_PMU_BC12_MANUAL (0x63) 130 #define MT6360_PMU_CHGDET_FUNC (0x64) 131 #define MT6360_PMU_FOD_CTRL (0x65) 132 #define MT6360_PMU_CHG_CTRL20 (0x66) 133 #define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) 134 #define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) 135 #define MT6360_PMU_RESV2 (0x69) 136 #define MT6360_PMU_USBID_CTRL1 (0x6D) 137 #define MT6360_PMU_USBID_CTRL2 (0x6E) 138 #define MT6360_PMU_USBID_CTRL3 (0x6F) 139 #define MT6360_PMU_FLED_CFG (0x70) 140 #define MT6360_PMU_RESV3 (0x71) 141 #define MT6360_PMU_FLED1_CTRL (0x72) 142 #define MT6360_PMU_FLED_STRB_CTRL (0x73) 143 #define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) 144 #define MT6360_PMU_FLED1_TOR_CTRL (0x75) 145 #define MT6360_PMU_FLED2_CTRL (0x76) 146 #define MT6360_PMU_RESV4 (0x77) 147 #define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) 148 #define MT6360_PMU_FLED2_TOR_CTRL (0x79) 149 #define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) 150 #define MT6360_PMU_FLED_VMID_RTM (0x7B) 151 #define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) 152 #define MT6360_PMU_FLED_PWSEL (0x7D) 153 #define MT6360_PMU_FLED_EN (0x7E) 154 #define MT6360_PMU_FLED_Hidden1 (0x7F) 155 #define MT6360_PMU_RGB_EN (0x80) 156 #define MT6360_PMU_RGB1_ISNK (0x81) 157 #define MT6360_PMU_RGB2_ISNK (0x82) 158 #define MT6360_PMU_RGB3_ISNK (0x83) 159 #define MT6360_PMU_RGB_ML_ISNK (0x84) 160 #define MT6360_PMU_RGB1_DIM (0x85) 161 #define MT6360_PMU_RGB2_DIM (0x86) 162 #define MT6360_PMU_RGB3_DIM (0x87) 163 #define MT6360_PMU_RESV5 (0x88) 164 #define MT6360_PMU_RGB12_Freq (0x89) 165 #define MT6360_PMU_RGB34_Freq (0x8A) 166 #define MT6360_PMU_RGB1_Tr (0x8B) 167 #define MT6360_PMU_RGB1_Tf (0x8C) 168 #define MT6360_PMU_RGB1_TON_TOFF (0x8D) 169 #define MT6360_PMU_RGB2_Tr (0x8E) 170 #define MT6360_PMU_RGB2_Tf (0x8F) 171 #define MT6360_PMU_RGB2_TON_TOFF (0x90) 172 #define MT6360_PMU_RGB3_Tr (0x91) 173 #define MT6360_PMU_RGB3_Tf (0x92) 174 #define MT6360_PMU_RGB3_TON_TOFF (0x93) 175 #define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) 176 #define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) 177 #define MT6360_PMU_RESV6 (0x97) 178 #define MT6360_PMU_SPARE1 (0x9A) 179 #define MT6360_PMU_SPARE2 (0xA0) 180 #define MT6360_PMU_SPARE3 (0xB0) 181 #define MT6360_PMU_SPARE4 (0xC0) 182 #define MT6360_PMU_CHG_IRQ1 (0xD0) 183 #define MT6360_PMU_CHG_IRQ2 (0xD1) 184 #define MT6360_PMU_CHG_IRQ3 (0xD2) 185 #define MT6360_PMU_CHG_IRQ4 (0xD3) 186 #define MT6360_PMU_CHG_IRQ5 (0xD4) 187 #define MT6360_PMU_CHG_IRQ6 (0xD5) 188 #define MT6360_PMU_QC_IRQ (0xD6) 189 #define MT6360_PMU_FOD_IRQ (0xD7) 190 #define MT6360_PMU_BASE_IRQ (0xD8) 191 #define MT6360_PMU_FLED_IRQ1 (0xD9) 192 #define MT6360_PMU_FLED_IRQ2 (0xDA) 193 #define MT6360_PMU_RGB_IRQ (0xDB) 194 #define MT6360_PMU_BUCK1_IRQ (0xDC) 195 #define MT6360_PMU_BUCK2_IRQ (0xDD) 196 #define MT6360_PMU_LDO_IRQ1 (0xDE) 197 #define MT6360_PMU_LDO_IRQ2 (0xDF) 198 #define MT6360_PMU_CHG_STAT1 (0xE0) 199 #define MT6360_PMU_CHG_STAT2 (0xE1) 200 #define MT6360_PMU_CHG_STAT3 (0xE2) 201 #define MT6360_PMU_CHG_STAT4 (0xE3) 202 #define MT6360_PMU_CHG_STAT5 (0xE4) 203 #define MT6360_PMU_CHG_STAT6 (0xE5) 204 #define MT6360_PMU_QC_STAT (0xE6) 205 #define MT6360_PMU_FOD_STAT (0xE7) 206 #define MT6360_PMU_BASE_STAT (0xE8) 207 #define MT6360_PMU_FLED_STAT1 (0xE9) 208 #define MT6360_PMU_FLED_STAT2 (0xEA) 209 #define MT6360_PMU_RGB_STAT (0xEB) 210 #define MT6360_PMU_BUCK1_STAT (0xEC) 211 #define MT6360_PMU_BUCK2_STAT (0xED) 212 #define MT6360_PMU_LDO_STAT1 (0xEE) 213 #define MT6360_PMU_LDO_STAT2 (0xEF) 214 #define MT6360_PMU_CHG_MASK1 (0xF0) 215 #define MT6360_PMU_CHG_MASK2 (0xF1) 216 #define MT6360_PMU_CHG_MASK3 (0xF2) 217 #define MT6360_PMU_CHG_MASK4 (0xF3) 218 #define MT6360_PMU_CHG_MASK5 (0xF4) 219 #define MT6360_PMU_CHG_MASK6 (0xF5) 220 #define MT6360_PMU_QC_MASK (0xF6) 221 #define MT6360_PMU_FOD_MASK (0xF7) 222 #define MT6360_PMU_BASE_MASK (0xF8) 223 #define MT6360_PMU_FLED_MASK1 (0xF9) 224 #define MT6360_PMU_FLED_MASK2 (0xFA) 225 #define MT6360_PMU_FAULTB_MASK (0xFB) 226 #define MT6360_PMU_BUCK1_MASK (0xFC) 227 #define MT6360_PMU_BUCK2_MASK (0xFD) 228 #define MT6360_PMU_LDO_MASK1 (0xFE) 229 #define MT6360_PMU_LDO_MASK2 (0xFF) 230 #define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) 231 232 /* MT6360_PMU_IRQ_SET */ 233 #define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) 234 #define MT6360_IRQ_RETRIG BIT(2) 235 236 #define CHIP_VEN_MASK (0xF0) 237 #define CHIP_VEN_MT6360 (0x50) 238 #define CHIP_REV_MASK (0x0F) 239 240 #endif /* __MT6360_H__ */ 241