Searched refs:REG_DSI_28nm_8960_PHY_PLL_CTRL_1 (Results 1 – 2 of 2) sorted by relevance
123 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, in dsi_pll_28nm_clk_set_rate()174 fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); in dsi_pll_28nm_clk_recalc_rate()
917 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 macro