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Searched refs:REG_GET_FIELD (Results 1 – 25 of 45) sorted by relevance

12

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dumc_v8_7.c128 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
138 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
144 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && in umc_v8_7_query_correctable_error_count()
145 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_query_correctable_error_count()
146 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_7_query_correctable_error_count()
161 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_7_querry_uncorrectable_error_count()
162 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
163 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
164 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
165 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
[all …]
Dumc_v6_1.c81 return REG_GET_FIELD(rsmu_umc_val, in umc_v6_1_get_umc_index_mode_state()
203 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
213 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
219 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && in umc_v6_1_query_correctable_error_count()
220 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_correctable_error_count()
221 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_1_query_correctable_error_count()
244 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_1_querry_uncorrectable_error_count()
245 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
246 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
247 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
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Dsmu_v11_0_i2c.c142 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); in smu_v11_0_i2c_poll_tx_status()
150 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { in smu_v11_0_i2c_poll_tx_status()
155 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
161 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
185 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_rx_status()
203 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); in smu_v11_0_i2c_poll_rx_status()
253 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { in smu_v11_0_i2c_transmit()
280 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); in smu_v11_0_i2c_transmit()
379 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); in smu_v11_0_i2c_receive()
426 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && in smu_v11_0_i2c_activity_done()
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Dgfxhub_v1_1.c36 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
60 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v1_1_get_xgmi_info()
63 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
Dgfxhub_v2_1.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
503 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v2_1_get_xgmi_info()
523 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v2_1_get_xgmi_info()
527 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v2_1_get_xgmi_info()
Dgmc_v7_0.c97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v7_0_mc_stop()
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
772 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
773 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
779 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
784 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
[all …]
Dnbio_v7_4.c308 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_4_handle_ras_controller_intr_no_bifring()
357 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
497 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); in nbio_v7_4_query_ras_error_count()
498 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); in nbio_v7_4_query_ras_error_count()
499 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, in nbio_v7_4_query_ras_error_count()
518 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, in nbio_v7_4_query_ras_error_count()
Dgmc_v8_0.c185 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v8_0_mc_stop()
328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
1022 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
1023 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1029 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1034 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
[all …]
Dgfxhub_v2_0.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
Dcz_ih.c196 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
202 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
347 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
362 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
Diceland_ih.c196 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
202 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
346 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
361 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
Dgmc_v6_0.c71 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v6_0_mc_stop()
617 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
618 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
623 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
628 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
807 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v6_0_get_vbios_fb_size()
811 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v6_0_get_vbios_fb_size()
812 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v6_0_get_vbios_fb_size()
Dtonga_ih.c198 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
204 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
358 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_is_idle()
373 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_wait_for_idle()
Dgmc_v9_0.c556 cid = REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
558 rw = REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
614 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
617 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
620 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
623 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
1083 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
1092 size = (REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1094 REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1103 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v9_0_get_vbios_fb_size()
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Dmmhub_v2_0.c123 cid = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
125 rw = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
148 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
151 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
154 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
157 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
Dgfx_v9_4.c711 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
755 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
763 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
776 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
785 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
799 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
808 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
Damdgpu_amdkfd_gfx_v7.c455 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
459 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
460 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
467 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
685 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
Dgfx_v8_0.c1830 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1832 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1840 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1841 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1844 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1845 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1864 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
3467 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); in gfx_v8_0_get_rb_active_bitmap()
4876 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) in gfx_v8_0_is_idle()
4988 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v8_0_check_soft_reset()
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Damdgpu_amdkfd_gfx_v10.c269 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
581 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
585 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
586 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
593 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
Damdgpu_amdkfd_gfx_v8.c453 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
457 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
458 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
465 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
Ddf_v3_6.c282 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
285 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
288 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
Dvi.c336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) in vi_get_xclk()
340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) in vi_get_xclk()
1034 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); in vi_get_pcie_usage()
1035 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); in vi_get_pcie_usage()
1064 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in vi_need_reset_on_init()
Dgmc_v10_0.c582 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v10_0_get_vbios_fb_size()
590 size = (REG_GET_FIELD(viewport, in gmc_v10_0_get_vbios_fb_size()
592 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * in gmc_v10_0_get_vbios_fb_size()
Dsoc15.c907 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); in soc15_get_pcie_usage()
908 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); in soc15_get_pcie_usage()
956 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); in vega20_get_pcie_usage()
957 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); in vega20_get_pcie_usage()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_thermal.c105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
267 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_percent()

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