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Searched refs:REG_SET (Results 1 – 25 of 69) sorted by relevance

123

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubp.c61 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
64 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
120 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
124 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
133 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
149 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp3_program_surface_flip_and_addr()
153 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
157 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
161 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
[all …]
Ddcn30_dpp_cm.c100 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
102 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
108 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
110 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
112 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
117 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg); in dpp3_program_gammcor_lut()
119 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green); in dpp3_program_gammcor_lut()
121 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
126 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg); in dpp3_program_gammcor_lut()
128 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_blue); in dpp3_program_gammcor_lut()
[all …]
Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
200 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
210 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
220 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg); in dwb3_program_ogam_pwl()
[all …]
Ddcn30_optc.c48 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc3_triplebuffer_lock()
51 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc3_triplebuffer_lock()
109 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc3_lock()
158 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0, in optc3_set_vtotal_change_limit()
197 REG_SET(OTG_H_TIMING_CNTL, 0, in optc3_set_odm_bypass()
200 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc3_set_odm_bypass()
239 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc3_set_odm_combine()
259 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
Ddcn30_mpc.c69 REG_SET(DWB_MUX[dwb_id], 0, in mpc3_set_dwb_mux()
79 REG_SET(DWB_MUX[dwb_id], 0, in mpc3_disable_dwb_mux()
146 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc3_power_on_ogam_lut()
160 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc3_configure_ogam_lut()
283 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); in mpc3_program_ogam_pwl()
285 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_red); in mpc3_program_ogam_pwl()
293 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); in mpc3_program_ogam_pwl()
295 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_red); in mpc3_program_ogam_pwl()
297 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc3_program_ogam_pwl()
303 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg); in mpc3_program_ogam_pwl()
[all …]
Ddcn30_hubbub.c70 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub3_init_dchub_sys_ctx()
72 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub3_init_dchub_sys_ctx()
74 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub3_init_dchub_sys_ctx()
76 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub3_init_dchub_sys_ctx()
78 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub3_init_dchub_sys_ctx()
80 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub3_init_dchub_sys_ctx()
127 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub3_program_watermarks()
Ddcn30_dpp.c70 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0); in dpp3_program_post_csc()
123 REG_SET(CM_POST_CSC_CONTROL, 0, in dpp3_program_post_csc()
503 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp3_power_on_blnd_lut()
518 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); in dpp3_configure_blnd_lut()
534 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); in dpp3_program_blnd_pwl()
535 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); in dpp3_program_blnd_pwl()
539 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); in dpp3_program_blnd_pwl()
540 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); in dpp3_program_blnd_pwl()
544 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); in dpp3_program_blnd_pwl()
545 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green); in dpp3_program_blnd_pwl()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_mpc.c61 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
63 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
65 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
222 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
226 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
229 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
230 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
233 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane()
247 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); in mpc1_insert_plane()
313 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
[all …]
Ddcn10_hubp.c396 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
400 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
405 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
409 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
429 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
433 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
437 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
446 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
[all …]
Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
154 REG_SET( in program_gamut_remap()
201 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
235 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
323 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
338 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
339 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
340 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
342 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
343 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); in dpp1_cm_program_regamma_lut()
[all …]
Ddcn10_optc.c79 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
86 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
94 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, in optc1_setup_vertical_interrupt1()
130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, in optc1_setup_vertical_interrupt2()
172 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
203 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
209 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_program_timing()
211 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_program_timing()
645 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc1_lock()
[all …]
Ddcn10_hubbub.c261 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub1_program_urgent_watermarks()
286 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub1_program_urgent_watermarks()
311 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub1_program_urgent_watermarks()
336 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub1_program_urgent_watermarks()
377 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
393 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
410 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
426 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
443 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
459 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_vmid.c75 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
77 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
82 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
89 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
Ddcn20_mpc.c66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
143 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
183 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
199 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
242 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
279 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
294 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc20_configure_ogam_lut()
389 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); in mpc20_program_ogam_pwl()
[all …]
Ddcn20_hubp.c65 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, in hubp2_set_vm_system_aperture_settings()
68 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
71 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
91 REG_SET(BLANK_OFFSET_1, 0, in hubp2_program_deadline()
94 REG_SET(DST_DIMENSIONS, 0, in hubp2_program_deadline()
101 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, in hubp2_program_deadline()
105 REG_SET(VBLANK_PARAMETERS_1, 0, in hubp2_program_deadline()
109 REG_SET(NOM_PARAMETERS_0, 0, in hubp2_program_deadline()
113 REG_SET(NOM_PARAMETERS_1, 0, in hubp2_program_deadline()
116 REG_SET(NOM_PARAMETERS_4, 0, in hubp2_program_deadline()
[all …]
Ddcn20_dpp_cm.c99 REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); in dpp2_program_degamma_lut()
101 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); in dpp2_program_degamma_lut()
102 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); in dpp2_program_degamma_lut()
103 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); in dpp2_program_degamma_lut()
105 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
107 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
109 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
170 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
207 REG_SET( in program_gamut_remap()
252 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); in dpp2_program_input_csc()
[all …]
Ddcn20_optc.c202 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
230 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
261 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
272 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
316 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_triplebuffer_lock()
319 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_lock()
322 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_lock()
335 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_unlock()
338 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_unlock()
400 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, in optc2_program_manual_trigger()
Ddcn20_hubbub.c382 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub2_init_dchub_sys_ctx()
384 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub2_init_dchub_sys_ctx()
386 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub2_init_dchub_sys_ctx()
388 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub2_init_dchub_sys_ctx()
390 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub2_init_dchub_sys_ctx()
392 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub2_init_dchub_sys_ctx()
395 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubbub2_init_dchub_sys_ctx()
397 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, in hubbub2_init_dchub_sys_ctx()
603 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub2_program_watermarks()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_ipp.c129 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
132 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
180 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
183 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
195 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
199 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
202 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
205 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
212 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
154 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in dce60_setup_scaling_configuration()
226 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
344 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
347 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
367 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
370 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
445 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
460 REG_SET(SCL_HORZ_FILTER_CONTROL, 0, in dce_transform_set_scaler()
[all …]
Ddce_mem_input.c507 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
510 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
513 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
516 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
519 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
522 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
537 REG_SET(GRPH_X_START, 0, in dce60_program_size()
540 REG_SET(GRPH_Y_START, 0, in dce60_program_size()
543 REG_SET(GRPH_X_END, 0, in dce60_program_size()
546 REG_SET(GRPH_Y_END, 0, in dce60_program_size()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Danatop.c16 #define REG_SET 0x4 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.c111 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub21_init_dchub()
113 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub21_init_dchub()
115 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub21_init_dchub()
117 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub21_init_dchub()
119 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub21_init_dchub()
121 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub21_init_dchub()
170 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub21_program_urgent_watermarks()
180 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub21_program_urgent_watermarks()
190 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, in hubbub21_program_urgent_watermarks()
215 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub21_program_urgent_watermarks()
[all …]
Ddcn21_hubp.c93 REG_SET(VBLANK_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
101 REG_SET(VBLANK_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
109 REG_SET(FLIP_PARAMETERS_3, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
117 REG_SET(FLIP_PARAMETERS_4, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
120 REG_SET(FLIP_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
123 REG_SET(FLIP_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
240 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
243 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
616 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in program_surface_flip_and_addr()
620 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in program_surface_flip_and_addr()
[all …]
/kernel/linux/linux-5.10/drivers/thermal/
Dimx_thermal.c20 #define REG_SET 0x4 macro
227 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
247 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
683 regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, in imx_thermal_probe()
714 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
716 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
768 regmap_write(map, data->socdata->measure_freq_ctrl + REG_SET, in imx_thermal_probe()
777 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
876 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_suspend()
902 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_resume()

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