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Searched refs:REG_SET_2 (Results 1 – 25 of 40) sorted by relevance

12

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, in dpp1_dscl_set_overscan()
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, in dpp1_dscl_set_overscan()
124 REG_SET_2(OTG_H_BLANK, 0, in dpp1_dscl_set_otg_blank()
128 REG_SET_2(OTG_V_BLANK, 0, in dpp1_dscl_set_otg_blank()
223 REG_SET_2(LB_DATA_FORMAT, 0, in dpp1_dscl_set_lb()
228 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
386 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
561 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale()
566 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale()
603 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
[all …]
Ddcn10_hubp.c594 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline()
604 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline()
629 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline()
651 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline()
696 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_setup_interdependent()
703 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_setup_interdependent()
713 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_setup_interdependent()
726 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_setup_interdependent()
773 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings()
813 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_context0_settings()
[all …]
Ddcn10_cm_common.c56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices()
73 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func()
76 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func()
79 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func()
92 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func()
98 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func()
104 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
Ddcn10_optc.c82 REG_SET_2(OTG_VUPDATE_PARAM, 0, in optc1_program_global_sync()
97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, in optc1_disable_stereo()
109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, in optc1_setup_vertical_interrupt0()
853 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, in optc1_set_static_screen_control()
1096 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
1108 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_opp.c92 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
97 REG_SET_2(DPG_OFFSET_SEGMENT, 0, in opp2_set_disp_pattern_generator()
171 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_set_disp_pattern_generator()
174 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_set_disp_pattern_generator()
177 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_set_disp_pattern_generator()
282 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
301 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_dpg_set_blank_color()
304 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_dpg_set_blank_color()
307 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_dpg_set_blank_color()
Ddcn20_dpp_cm.c582 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
585 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
588 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
592 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
596 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
600 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
732 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
735 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, in dpp20_program_shaper_lutb_settings()
738 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, in dpp20_program_shaper_lutb_settings()
742 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
[all …]
Ddcn20_optc.c129 REG_SET_2(OTG_GSL_WINDOW_X, 0, in optc2_set_gsl_window()
132 REG_SET_2(OTG_GSL_WINDOW_Y, 0, in optc2_set_gsl_window()
182 REG_SET_2(OTG_DSC_START_POSITION, 0, in optc2_set_dsc_encoder_frame_start()
409 REG_SET_2(OTG_CRC_CNTL2, 0, in optc2_configure_crc()
Ddcn20_hubp.c74 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp2_set_vm_system_aperture_settings()
87 REG_SET_2(BLANK_OFFSET_0, 0, in hubp2_program_deadline()
97 REG_SET_2(DST_AFTER_SCALER, 0, in hubp2_program_deadline()
122 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp2_program_deadline()
144 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp2_program_deadline()
252 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp2_setup_interdependent()
259 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp2_setup_interdependent()
263 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp2_setup_interdependent()
276 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp2_setup_interdependent()
291 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp2_setup_interdependent()
[all …]
Ddcn20_stream_encoder.c173 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
183 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
193 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
203 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
Ddcn20_dsc.c558 REG_SET_2(DSCCIF_CONFIG1, 0, in dsc_write_to_registers()
600 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
604 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
611 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
620 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
624 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
628 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
Ddcn20_vmid.c85 REG_SET_2(CNTL, 0, in dcn20_vmid_setup()
Ddcn20_dccg.c64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_opp.c371 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
379 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
384 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
389 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
395 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
400 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping()
404 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping()
408 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping()
431 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
439 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
[all …]
Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
164 REG_SET_2(SCL_TAP_CONTROL, 0, in dce60_setup_scaling_configuration()
199 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan()
202 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan()
266 REG_SET_2(VIEWPORT_START, 0, in program_viewport()
270 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport()
350 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits()
354 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits()
374 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0, in dce60_program_scl_ratios_inits()
379 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0, in dce60_program_scl_ratios_inits()
[all …]
Ddce_ipp.c57 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position()
61 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position()
119 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes()
149 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale()
153 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale()
157 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale()
244 REG_SET_2(DEGAMMA_CONTROL, 0, in dce60_ipp_set_degamma()
Ddce_hwseq.c71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
Ddce_mem_input.c172 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in program_urgency_watermark()
187 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce60_program_urgency_watermark()
202 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce120_program_urgency_watermark()
206 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, in dce120_program_urgency_watermark()
575 REG_SET_2(GRPH_SWAP_CNTL, 0, in program_grph_pixel_format()
803 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, in program_sec_addr()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn30.c101 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn30_backdoor_load()
110 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn30_backdoor_load()
135 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
150 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
161 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
167 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
178 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
187 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
Ddmub_dcn20.c160 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn20_backdoor_load()
169 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn20_backdoor_load()
196 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
211 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
223 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
229 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
240 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
249 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.c155 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub21_program_urgent_watermarks()
200 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub21_program_urgent_watermarks()
245 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub21_program_urgent_watermarks()
290 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub21_program_urgent_watermarks()
351 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
368 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
386 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
403 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
421 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
438 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
[all …]
Ddcn21_hubp.c193 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport()
197 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, in hubp21_set_viewport()
202 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport()
206 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, in hubp21_set_viewport()
211 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport()
215 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, in hubp21_set_viewport()
219 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport()
223 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, in hubp21_set_viewport()
246 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp21_set_vm_system_aperture_settings()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c166 REG_SET_2(PRE_DEGAM, 0, in dpp3_set_pre_degam()
193 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
304 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
313 REG_SET_2(PRE_DEALPHA, 0, in dpp3_cnv_setup()
316 REG_SET_2(PRE_REALPHA, 0, in dpp3_cnv_setup()
786 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
789 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
792 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp3_program_shaper_luta_settings()
796 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
800 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
[all …]
Ddcn30_dio_stream_encoder.c243 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
253 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
263 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
273 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
283 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
293 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
303 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
308 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
Ddcn30_mpc.c471 REG_SET_2(SHAPER_RAMA_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
474 REG_SET_2(SHAPER_RAMA_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
477 REG_SET_2(SHAPER_RAMA_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
481 REG_SET_2(SHAPER_RAMA_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
484 REG_SET_2(SHAPER_RAMA_END_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
487 REG_SET_2(SHAPER_RAMA_END_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
620 REG_SET_2(SHAPER_RAMB_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
623 REG_SET_2(SHAPER_RAMB_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
626 REG_SET_2(SHAPER_RAMB_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
630 REG_SET_2(SHAPER_RAMB_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
[all …]
Ddcn30_cm_common.c51 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_gamcor_xfer_func()
54 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_gamcor_xfer_func()
57 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_gamcor_xfer_func()
75 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_gamcor_xfer_func()
78 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_gamcor_xfer_func()
81 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_gamcor_xfer_func()

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