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1  // SPDX-License-Identifier: GPL-2.0-or-later
2  /*
3   * DesignWare High-Definition Multimedia Interface (HDMI) driver
4   *
5   * Copyright (C) 2013-2015 Mentor Graphics Inc.
6   * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7   * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8   */
9  #include <linux/clk.h>
10  #include <linux/delay.h>
11  #include <linux/err.h>
12  #include <linux/hdmi.h>
13  #include <linux/irq.h>
14  #include <linux/module.h>
15  #include <linux/mutex.h>
16  #include <linux/of_device.h>
17  #include <linux/pinctrl/consumer.h>
18  #include <linux/regmap.h>
19  #include <linux/dma-mapping.h>
20  #include <linux/spinlock.h>
21  
22  #include <media/cec-notifier.h>
23  
24  #include <uapi/linux/media-bus-format.h>
25  #include <uapi/linux/videodev2.h>
26  
27  #include <drm/bridge/dw_hdmi.h>
28  #include <drm/drm_atomic.h>
29  #include <drm/drm_atomic_helper.h>
30  #include <drm/drm_bridge.h>
31  #include <drm/drm_edid.h>
32  #include <drm/drm_of.h>
33  #include <drm/drm_print.h>
34  #include <drm/drm_probe_helper.h>
35  #include <drm/drm_scdc_helper.h>
36  
37  #include "dw-hdmi-audio.h"
38  #include "dw-hdmi-cec.h"
39  #include "dw-hdmi.h"
40  
41  #define DDC_CI_ADDR		0x37
42  #define DDC_SEGMENT_ADDR	0x30
43  
44  #define HDMI_EDID_LEN		512
45  
46  /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
47  #define SCDC_MIN_SOURCE_VERSION	0x1
48  
49  #define HDMI14_MAX_TMDSCLK	340000000
50  
51  enum hdmi_datamap {
52  	RGB444_8B = 0x01,
53  	RGB444_10B = 0x03,
54  	RGB444_12B = 0x05,
55  	RGB444_16B = 0x07,
56  	YCbCr444_8B = 0x09,
57  	YCbCr444_10B = 0x0B,
58  	YCbCr444_12B = 0x0D,
59  	YCbCr444_16B = 0x0F,
60  	YCbCr422_8B = 0x16,
61  	YCbCr422_10B = 0x14,
62  	YCbCr422_12B = 0x12,
63  };
64  
65  static const u16 csc_coeff_default[3][4] = {
66  	{ 0x2000, 0x0000, 0x0000, 0x0000 },
67  	{ 0x0000, 0x2000, 0x0000, 0x0000 },
68  	{ 0x0000, 0x0000, 0x2000, 0x0000 }
69  };
70  
71  static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
72  	{ 0x2000, 0x6926, 0x74fd, 0x010e },
73  	{ 0x2000, 0x2cdd, 0x0000, 0x7e9a },
74  	{ 0x2000, 0x0000, 0x38b4, 0x7e3b }
75  };
76  
77  static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
78  	{ 0x2000, 0x7106, 0x7a02, 0x00a7 },
79  	{ 0x2000, 0x3264, 0x0000, 0x7e6d },
80  	{ 0x2000, 0x0000, 0x3b61, 0x7e25 }
81  };
82  
83  static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
84  	{ 0x2591, 0x1322, 0x074b, 0x0000 },
85  	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
86  	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
87  };
88  
89  static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
90  	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
91  	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
92  	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
93  };
94  
95  static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
96  	{ 0x1b7c, 0x0000, 0x0000, 0x0020 },
97  	{ 0x0000, 0x1b7c, 0x0000, 0x0020 },
98  	{ 0x0000, 0x0000, 0x1b7c, 0x0020 }
99  };
100  
101  struct hdmi_vmode {
102  	bool mdataenablepolarity;
103  
104  	unsigned int mpixelclock;
105  	unsigned int mpixelrepetitioninput;
106  	unsigned int mpixelrepetitionoutput;
107  	unsigned int mtmdsclock;
108  };
109  
110  struct hdmi_data_info {
111  	unsigned int enc_in_bus_format;
112  	unsigned int enc_out_bus_format;
113  	unsigned int enc_in_encoding;
114  	unsigned int enc_out_encoding;
115  	unsigned int pix_repet_factor;
116  	unsigned int hdcp_enable;
117  	struct hdmi_vmode video_mode;
118  	bool rgb_limited_range;
119  };
120  
121  struct dw_hdmi_i2c {
122  	struct i2c_adapter	adap;
123  
124  	struct mutex		lock;	/* used to serialize data transfers */
125  	struct completion	cmp;
126  	u8			stat;
127  
128  	u8			slave_reg;
129  	bool			is_regaddr;
130  	bool			is_segment;
131  };
132  
133  struct dw_hdmi_phy_data {
134  	enum dw_hdmi_phy_type type;
135  	const char *name;
136  	unsigned int gen;
137  	bool has_svsret;
138  	int (*configure)(struct dw_hdmi *hdmi,
139  			 const struct dw_hdmi_plat_data *pdata,
140  			 unsigned long mpixelclock);
141  };
142  
143  struct dw_hdmi {
144  	struct drm_connector connector;
145  	struct drm_bridge bridge;
146  
147  	unsigned int version;
148  
149  	struct platform_device *audio;
150  	struct platform_device *cec;
151  	struct device *dev;
152  	struct clk *isfr_clk;
153  	struct clk *iahb_clk;
154  	struct clk *cec_clk;
155  	struct dw_hdmi_i2c *i2c;
156  
157  	struct hdmi_data_info hdmi_data;
158  	const struct dw_hdmi_plat_data *plat_data;
159  
160  	int vic;
161  
162  	u8 edid[HDMI_EDID_LEN];
163  
164  	struct {
165  		const struct dw_hdmi_phy_ops *ops;
166  		const char *name;
167  		void *data;
168  		bool enabled;
169  	} phy;
170  
171  	struct drm_display_mode previous_mode;
172  
173  	struct i2c_adapter *ddc;
174  	void __iomem *regs;
175  	bool sink_is_hdmi;
176  	bool sink_has_audio;
177  
178  	struct pinctrl *pinctrl;
179  	struct pinctrl_state *default_state;
180  	struct pinctrl_state *unwedge_state;
181  
182  	struct mutex mutex;		/* for state below and previous_mode */
183  	enum drm_connector_force force;	/* mutex-protected force state */
184  	struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
185  	bool disabled;			/* DRM has disabled our bridge */
186  	bool bridge_is_on;		/* indicates the bridge is on */
187  	bool rxsense;			/* rxsense state */
188  	u8 phy_mask;			/* desired phy int mask settings */
189  	u8 mc_clkdis;			/* clock disable register */
190  
191  	spinlock_t audio_lock;
192  	struct mutex audio_mutex;
193  	unsigned int sample_rate;
194  	unsigned int audio_cts;
195  	unsigned int audio_n;
196  	bool audio_enable;
197  
198  	unsigned int reg_shift;
199  	struct regmap *regm;
200  	void (*enable_audio)(struct dw_hdmi *hdmi);
201  	void (*disable_audio)(struct dw_hdmi *hdmi);
202  
203  	struct mutex cec_notifier_mutex;
204  	struct cec_notifier *cec_notifier;
205  
206  	hdmi_codec_plugged_cb plugged_cb;
207  	struct device *codec_dev;
208  	enum drm_connector_status last_connector_result;
209  };
210  
211  #define HDMI_IH_PHY_STAT0_RX_SENSE \
212  	(HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
213  	 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
214  
215  #define HDMI_PHY_RX_SENSE \
216  	(HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
217  	 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
218  
hdmi_writeb(struct dw_hdmi * hdmi,u8 val,int offset)219  static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
220  {
221  	regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
222  }
223  
hdmi_readb(struct dw_hdmi * hdmi,int offset)224  static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
225  {
226  	unsigned int val = 0;
227  
228  	regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
229  
230  	return val;
231  }
232  
handle_plugged_change(struct dw_hdmi * hdmi,bool plugged)233  static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
234  {
235  	if (hdmi->plugged_cb && hdmi->codec_dev)
236  		hdmi->plugged_cb(hdmi->codec_dev, plugged);
237  }
238  
dw_hdmi_set_plugged_cb(struct dw_hdmi * hdmi,hdmi_codec_plugged_cb fn,struct device * codec_dev)239  int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
240  			   struct device *codec_dev)
241  {
242  	bool plugged;
243  
244  	mutex_lock(&hdmi->mutex);
245  	hdmi->plugged_cb = fn;
246  	hdmi->codec_dev = codec_dev;
247  	plugged = hdmi->last_connector_result == connector_status_connected;
248  	handle_plugged_change(hdmi, plugged);
249  	mutex_unlock(&hdmi->mutex);
250  
251  	return 0;
252  }
253  EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
254  
hdmi_modb(struct dw_hdmi * hdmi,u8 data,u8 mask,unsigned reg)255  static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
256  {
257  	regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
258  }
259  
hdmi_mask_writeb(struct dw_hdmi * hdmi,u8 data,unsigned int reg,u8 shift,u8 mask)260  static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
261  			     u8 shift, u8 mask)
262  {
263  	hdmi_modb(hdmi, data << shift, mask, reg);
264  }
265  
dw_hdmi_i2c_init(struct dw_hdmi * hdmi)266  static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
267  {
268  	hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
269  		    HDMI_PHY_I2CM_INT_ADDR);
270  
271  	hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
272  		    HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
273  		    HDMI_PHY_I2CM_CTLINT_ADDR);
274  
275  	/* Software reset */
276  	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
277  
278  	/* Set Standard Mode speed (determined to be 100KHz on iMX6) */
279  	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
280  
281  	/* Set done, not acknowledged and arbitration interrupt polarities */
282  	hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
283  	hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
284  		    HDMI_I2CM_CTLINT);
285  
286  	/* Clear DONE and ERROR interrupts */
287  	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
288  		    HDMI_IH_I2CM_STAT0);
289  
290  	/* Mute DONE and ERROR interrupts */
291  	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
292  		    HDMI_IH_MUTE_I2CM_STAT0);
293  }
294  
dw_hdmi_i2c_unwedge(struct dw_hdmi * hdmi)295  static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
296  {
297  	/* If no unwedge state then give up */
298  	if (!hdmi->unwedge_state)
299  		return false;
300  
301  	dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
302  
303  	/*
304  	 * This is a huge hack to workaround a problem where the dw_hdmi i2c
305  	 * bus could sometimes get wedged.  Once wedged there doesn't appear
306  	 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
307  	 * other than pulsing the SDA line.
308  	 *
309  	 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
310  	 * by:
311  	 * 1. Remux the pin as a GPIO output, driven low.
312  	 * 2. Wait a little while.  1 ms seems to work, but we'll do 10.
313  	 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
314  	 *
315  	 * At the moment of remuxing, the line will still be low due to its
316  	 * recent stint as an output, but then it will be pulled high by the
317  	 * (presumed) external pullup.  dw_hdmi seems to see this as a rising
318  	 * edge and that seems to get it out of its jam.
319  	 *
320  	 * This wedging was only ever seen on one TV, and only on one of
321  	 * its HDMI ports.  It happened when the TV was powered on while the
322  	 * device was plugged in.  A scope trace shows the TV bringing both SDA
323  	 * and SCL low, then bringing them both back up at roughly the same
324  	 * time.  Presumably this confuses dw_hdmi because it saw activity but
325  	 * no real STOP (maybe it thinks there's another master on the bus?).
326  	 * Giving it a clean rising edge of SDA while SCL is already high
327  	 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
328  	 * of its stupor.
329  	 *
330  	 * Note that after coming back alive, transfers seem to immediately
331  	 * resume, so if we unwedge due to a timeout we should wait a little
332  	 * longer for our transfer to finish, since it might have just started
333  	 * now.
334  	 */
335  	pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
336  	msleep(10);
337  	pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
338  
339  	return true;
340  }
341  
dw_hdmi_i2c_wait(struct dw_hdmi * hdmi)342  static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
343  {
344  	struct dw_hdmi_i2c *i2c = hdmi->i2c;
345  	int stat;
346  
347  	stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
348  	if (!stat) {
349  		/* If we can't unwedge, return timeout */
350  		if (!dw_hdmi_i2c_unwedge(hdmi))
351  			return -EAGAIN;
352  
353  		/* We tried to unwedge; give it another chance */
354  		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
355  		if (!stat)
356  			return -EAGAIN;
357  	}
358  
359  	/* Check for error condition on the bus */
360  	if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
361  		return -EIO;
362  
363  	return 0;
364  }
365  
dw_hdmi_i2c_read(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)366  static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
367  			    unsigned char *buf, unsigned int length)
368  {
369  	struct dw_hdmi_i2c *i2c = hdmi->i2c;
370  	int ret;
371  
372  	if (!i2c->is_regaddr) {
373  		dev_dbg(hdmi->dev, "set read register address to 0\n");
374  		i2c->slave_reg = 0x00;
375  		i2c->is_regaddr = true;
376  	}
377  
378  	while (length--) {
379  		reinit_completion(&i2c->cmp);
380  
381  		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
382  		if (i2c->is_segment)
383  			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
384  				    HDMI_I2CM_OPERATION);
385  		else
386  			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
387  				    HDMI_I2CM_OPERATION);
388  
389  		ret = dw_hdmi_i2c_wait(hdmi);
390  		if (ret)
391  			return ret;
392  
393  		*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
394  	}
395  	i2c->is_segment = false;
396  
397  	return 0;
398  }
399  
dw_hdmi_i2c_write(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)400  static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
401  			     unsigned char *buf, unsigned int length)
402  {
403  	struct dw_hdmi_i2c *i2c = hdmi->i2c;
404  	int ret;
405  
406  	if (!i2c->is_regaddr) {
407  		/* Use the first write byte as register address */
408  		i2c->slave_reg = buf[0];
409  		length--;
410  		buf++;
411  		i2c->is_regaddr = true;
412  	}
413  
414  	while (length--) {
415  		reinit_completion(&i2c->cmp);
416  
417  		hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
418  		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
419  		hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
420  			    HDMI_I2CM_OPERATION);
421  
422  		ret = dw_hdmi_i2c_wait(hdmi);
423  		if (ret)
424  			return ret;
425  	}
426  
427  	return 0;
428  }
429  
dw_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)430  static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
431  			    struct i2c_msg *msgs, int num)
432  {
433  	struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
434  	struct dw_hdmi_i2c *i2c = hdmi->i2c;
435  	u8 addr = msgs[0].addr;
436  	int i, ret = 0;
437  
438  	if (addr == DDC_CI_ADDR)
439  		/*
440  		 * The internal I2C controller does not support the multi-byte
441  		 * read and write operations needed for DDC/CI.
442  		 * TOFIX: Blacklist the DDC/CI address until we filter out
443  		 * unsupported I2C operations.
444  		 */
445  		return -EOPNOTSUPP;
446  
447  	dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
448  
449  	for (i = 0; i < num; i++) {
450  		if (msgs[i].len == 0) {
451  			dev_dbg(hdmi->dev,
452  				"unsupported transfer %d/%d, no data\n",
453  				i + 1, num);
454  			return -EOPNOTSUPP;
455  		}
456  	}
457  
458  	mutex_lock(&i2c->lock);
459  
460  	/* Unmute DONE and ERROR interrupts */
461  	hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
462  
463  	/* Set slave device address taken from the first I2C message */
464  	hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
465  
466  	/* Set slave device register address on transfer */
467  	i2c->is_regaddr = false;
468  
469  	/* Set segment pointer for I2C extended read mode operation */
470  	i2c->is_segment = false;
471  
472  	for (i = 0; i < num; i++) {
473  		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
474  			i + 1, num, msgs[i].len, msgs[i].flags);
475  		if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
476  			i2c->is_segment = true;
477  			hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
478  			hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
479  		} else {
480  			if (msgs[i].flags & I2C_M_RD)
481  				ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
482  						       msgs[i].len);
483  			else
484  				ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
485  							msgs[i].len);
486  		}
487  		if (ret < 0)
488  			break;
489  	}
490  
491  	if (!ret)
492  		ret = num;
493  
494  	/* Mute DONE and ERROR interrupts */
495  	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
496  		    HDMI_IH_MUTE_I2CM_STAT0);
497  
498  	mutex_unlock(&i2c->lock);
499  
500  	return ret;
501  }
502  
dw_hdmi_i2c_func(struct i2c_adapter * adapter)503  static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
504  {
505  	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
506  }
507  
508  static const struct i2c_algorithm dw_hdmi_algorithm = {
509  	.master_xfer	= dw_hdmi_i2c_xfer,
510  	.functionality	= dw_hdmi_i2c_func,
511  };
512  
dw_hdmi_i2c_adapter(struct dw_hdmi * hdmi)513  static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
514  {
515  	struct i2c_adapter *adap;
516  	struct dw_hdmi_i2c *i2c;
517  	int ret;
518  
519  	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
520  	if (!i2c)
521  		return ERR_PTR(-ENOMEM);
522  
523  	mutex_init(&i2c->lock);
524  	init_completion(&i2c->cmp);
525  
526  	adap = &i2c->adap;
527  	adap->class = I2C_CLASS_DDC;
528  	adap->owner = THIS_MODULE;
529  	adap->dev.parent = hdmi->dev;
530  	adap->algo = &dw_hdmi_algorithm;
531  	strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
532  	i2c_set_adapdata(adap, hdmi);
533  
534  	ret = i2c_add_adapter(adap);
535  	if (ret) {
536  		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
537  		devm_kfree(hdmi->dev, i2c);
538  		return ERR_PTR(ret);
539  	}
540  
541  	hdmi->i2c = i2c;
542  
543  	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
544  
545  	return adap;
546  }
547  
hdmi_set_cts_n(struct dw_hdmi * hdmi,unsigned int cts,unsigned int n)548  static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
549  			   unsigned int n)
550  {
551  	/* Must be set/cleared first */
552  	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
553  
554  	/* nshift factor = 0 */
555  	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
556  
557  	/* Use automatic CTS generation mode when CTS is not set */
558  	if (cts)
559  		hdmi_writeb(hdmi, ((cts >> 16) &
560  				   HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
561  				  HDMI_AUD_CTS3_CTS_MANUAL,
562  			    HDMI_AUD_CTS3);
563  	else
564  		hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
565  	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
566  	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
567  
568  	hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
569  	hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
570  	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
571  }
572  
hdmi_compute_n(unsigned int freq,unsigned long pixel_clk)573  static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
574  {
575  	unsigned int n = (128 * freq) / 1000;
576  	unsigned int mult = 1;
577  
578  	while (freq > 48000) {
579  		mult *= 2;
580  		freq /= 2;
581  	}
582  
583  	switch (freq) {
584  	case 32000:
585  		if (pixel_clk == 25175000)
586  			n = 4576;
587  		else if (pixel_clk == 27027000)
588  			n = 4096;
589  		else if (pixel_clk == 74176000 || pixel_clk == 148352000)
590  			n = 11648;
591  		else
592  			n = 4096;
593  		n *= mult;
594  		break;
595  
596  	case 44100:
597  		if (pixel_clk == 25175000)
598  			n = 7007;
599  		else if (pixel_clk == 74176000)
600  			n = 17836;
601  		else if (pixel_clk == 148352000)
602  			n = 8918;
603  		else
604  			n = 6272;
605  		n *= mult;
606  		break;
607  
608  	case 48000:
609  		if (pixel_clk == 25175000)
610  			n = 6864;
611  		else if (pixel_clk == 27027000)
612  			n = 6144;
613  		else if (pixel_clk == 74176000)
614  			n = 11648;
615  		else if (pixel_clk == 148352000)
616  			n = 5824;
617  		else
618  			n = 6144;
619  		n *= mult;
620  		break;
621  
622  	default:
623  		break;
624  	}
625  
626  	return n;
627  }
628  
629  /*
630   * When transmitting IEC60958 linear PCM audio, these registers allow to
631   * configure the channel status information of all the channel status
632   * bits in the IEC60958 frame. For the moment this configuration is only
633   * used when the I2S audio interface, General Purpose Audio (GPA),
634   * or AHB audio DMA (AHBAUDDMA) interface is active
635   * (for S/PDIF interface this information comes from the stream).
636   */
dw_hdmi_set_channel_status(struct dw_hdmi * hdmi,u8 * channel_status)637  void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
638  				u8 *channel_status)
639  {
640  	/*
641  	 * Set channel status register for frequency and word length.
642  	 * Use default values for other registers.
643  	 */
644  	hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
645  	hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
646  }
647  EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
648  
hdmi_set_clk_regenerator(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned int sample_rate)649  static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
650  	unsigned long pixel_clk, unsigned int sample_rate)
651  {
652  	unsigned long ftdms = pixel_clk;
653  	unsigned int n, cts;
654  	u8 config3;
655  	u64 tmp;
656  
657  	n = hdmi_compute_n(sample_rate, pixel_clk);
658  
659  	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
660  
661  	/* Only compute CTS when using internal AHB audio */
662  	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
663  		/*
664  		 * Compute the CTS value from the N value.  Note that CTS and N
665  		 * can be up to 20 bits in total, so we need 64-bit math.  Also
666  		 * note that our TDMS clock is not fully accurate; it is
667  		 * accurate to kHz.  This can introduce an unnecessary remainder
668  		 * in the calculation below, so we don't try to warn about that.
669  		 */
670  		tmp = (u64)ftdms * n;
671  		do_div(tmp, 128 * sample_rate);
672  		cts = tmp;
673  
674  		dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
675  			__func__, sample_rate,
676  			ftdms / 1000000, (ftdms / 1000) % 1000,
677  			n, cts);
678  	} else {
679  		cts = 0;
680  	}
681  
682  	spin_lock_irq(&hdmi->audio_lock);
683  	hdmi->audio_n = n;
684  	hdmi->audio_cts = cts;
685  	hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
686  	spin_unlock_irq(&hdmi->audio_lock);
687  }
688  
hdmi_init_clk_regenerator(struct dw_hdmi * hdmi)689  static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
690  {
691  	mutex_lock(&hdmi->audio_mutex);
692  	hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
693  	mutex_unlock(&hdmi->audio_mutex);
694  }
695  
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi * hdmi)696  static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
697  {
698  	mutex_lock(&hdmi->audio_mutex);
699  	hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
700  				 hdmi->sample_rate);
701  	mutex_unlock(&hdmi->audio_mutex);
702  }
703  
dw_hdmi_set_sample_rate(struct dw_hdmi * hdmi,unsigned int rate)704  void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
705  {
706  	mutex_lock(&hdmi->audio_mutex);
707  	hdmi->sample_rate = rate;
708  	hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
709  				 hdmi->sample_rate);
710  	mutex_unlock(&hdmi->audio_mutex);
711  }
712  EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
713  
dw_hdmi_set_channel_count(struct dw_hdmi * hdmi,unsigned int cnt)714  void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
715  {
716  	u8 layout;
717  
718  	mutex_lock(&hdmi->audio_mutex);
719  
720  	/*
721  	 * For >2 channel PCM audio, we need to select layout 1
722  	 * and set an appropriate channel map.
723  	 */
724  	if (cnt > 2)
725  		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
726  	else
727  		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
728  
729  	hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
730  		  HDMI_FC_AUDSCONF);
731  
732  	/* Set the audio infoframes channel count */
733  	hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
734  		  HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
735  
736  	mutex_unlock(&hdmi->audio_mutex);
737  }
738  EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
739  
dw_hdmi_set_channel_allocation(struct dw_hdmi * hdmi,unsigned int ca)740  void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
741  {
742  	mutex_lock(&hdmi->audio_mutex);
743  
744  	hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
745  
746  	mutex_unlock(&hdmi->audio_mutex);
747  }
748  EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
749  
hdmi_enable_audio_clk(struct dw_hdmi * hdmi,bool enable)750  static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
751  {
752  	if (enable)
753  		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
754  	else
755  		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
756  	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
757  }
758  
hdmi_audio_get_eld(struct dw_hdmi * hdmi)759  static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
760  {
761  	if (!hdmi->curr_conn)
762  		return NULL;
763  
764  	return hdmi->curr_conn->eld;
765  }
766  
dw_hdmi_ahb_audio_enable(struct dw_hdmi * hdmi)767  static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
768  {
769  	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
770  }
771  
dw_hdmi_ahb_audio_disable(struct dw_hdmi * hdmi)772  static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
773  {
774  	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
775  }
776  
dw_hdmi_i2s_audio_enable(struct dw_hdmi * hdmi)777  static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
778  {
779  	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
780  	hdmi_enable_audio_clk(hdmi, true);
781  }
782  
dw_hdmi_i2s_audio_disable(struct dw_hdmi * hdmi)783  static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
784  {
785  	hdmi_enable_audio_clk(hdmi, false);
786  }
787  
dw_hdmi_audio_enable(struct dw_hdmi * hdmi)788  void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
789  {
790  	unsigned long flags;
791  
792  	spin_lock_irqsave(&hdmi->audio_lock, flags);
793  	hdmi->audio_enable = true;
794  	if (hdmi->enable_audio)
795  		hdmi->enable_audio(hdmi);
796  	spin_unlock_irqrestore(&hdmi->audio_lock, flags);
797  }
798  EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
799  
dw_hdmi_audio_disable(struct dw_hdmi * hdmi)800  void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
801  {
802  	unsigned long flags;
803  
804  	spin_lock_irqsave(&hdmi->audio_lock, flags);
805  	hdmi->audio_enable = false;
806  	if (hdmi->disable_audio)
807  		hdmi->disable_audio(hdmi);
808  	spin_unlock_irqrestore(&hdmi->audio_lock, flags);
809  }
810  EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
811  
hdmi_bus_fmt_is_rgb(unsigned int bus_format)812  static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
813  {
814  	switch (bus_format) {
815  	case MEDIA_BUS_FMT_RGB888_1X24:
816  	case MEDIA_BUS_FMT_RGB101010_1X30:
817  	case MEDIA_BUS_FMT_RGB121212_1X36:
818  	case MEDIA_BUS_FMT_RGB161616_1X48:
819  		return true;
820  
821  	default:
822  		return false;
823  	}
824  }
825  
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)826  static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
827  {
828  	switch (bus_format) {
829  	case MEDIA_BUS_FMT_YUV8_1X24:
830  	case MEDIA_BUS_FMT_YUV10_1X30:
831  	case MEDIA_BUS_FMT_YUV12_1X36:
832  	case MEDIA_BUS_FMT_YUV16_1X48:
833  		return true;
834  
835  	default:
836  		return false;
837  	}
838  }
839  
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)840  static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
841  {
842  	switch (bus_format) {
843  	case MEDIA_BUS_FMT_UYVY8_1X16:
844  	case MEDIA_BUS_FMT_UYVY10_1X20:
845  	case MEDIA_BUS_FMT_UYVY12_1X24:
846  		return true;
847  
848  	default:
849  		return false;
850  	}
851  }
852  
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)853  static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
854  {
855  	switch (bus_format) {
856  	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
857  	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
858  	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
859  	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
860  		return true;
861  
862  	default:
863  		return false;
864  	}
865  }
866  
hdmi_bus_fmt_color_depth(unsigned int bus_format)867  static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
868  {
869  	switch (bus_format) {
870  	case MEDIA_BUS_FMT_RGB888_1X24:
871  	case MEDIA_BUS_FMT_YUV8_1X24:
872  	case MEDIA_BUS_FMT_UYVY8_1X16:
873  	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
874  		return 8;
875  
876  	case MEDIA_BUS_FMT_RGB101010_1X30:
877  	case MEDIA_BUS_FMT_YUV10_1X30:
878  	case MEDIA_BUS_FMT_UYVY10_1X20:
879  	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
880  		return 10;
881  
882  	case MEDIA_BUS_FMT_RGB121212_1X36:
883  	case MEDIA_BUS_FMT_YUV12_1X36:
884  	case MEDIA_BUS_FMT_UYVY12_1X24:
885  	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
886  		return 12;
887  
888  	case MEDIA_BUS_FMT_RGB161616_1X48:
889  	case MEDIA_BUS_FMT_YUV16_1X48:
890  	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
891  		return 16;
892  
893  	default:
894  		return 0;
895  	}
896  }
897  
898  /*
899   * this submodule is responsible for the video data synchronization.
900   * for example, for RGB 4:4:4 input, the data map is defined as
901   *			pin{47~40} <==> R[7:0]
902   *			pin{31~24} <==> G[7:0]
903   *			pin{15~8}  <==> B[7:0]
904   */
hdmi_video_sample(struct dw_hdmi * hdmi)905  static void hdmi_video_sample(struct dw_hdmi *hdmi)
906  {
907  	int color_format = 0;
908  	u8 val;
909  
910  	switch (hdmi->hdmi_data.enc_in_bus_format) {
911  	case MEDIA_BUS_FMT_RGB888_1X24:
912  		color_format = 0x01;
913  		break;
914  	case MEDIA_BUS_FMT_RGB101010_1X30:
915  		color_format = 0x03;
916  		break;
917  	case MEDIA_BUS_FMT_RGB121212_1X36:
918  		color_format = 0x05;
919  		break;
920  	case MEDIA_BUS_FMT_RGB161616_1X48:
921  		color_format = 0x07;
922  		break;
923  
924  	case MEDIA_BUS_FMT_YUV8_1X24:
925  	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
926  		color_format = 0x09;
927  		break;
928  	case MEDIA_BUS_FMT_YUV10_1X30:
929  	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
930  		color_format = 0x0B;
931  		break;
932  	case MEDIA_BUS_FMT_YUV12_1X36:
933  	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
934  		color_format = 0x0D;
935  		break;
936  	case MEDIA_BUS_FMT_YUV16_1X48:
937  	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
938  		color_format = 0x0F;
939  		break;
940  
941  	case MEDIA_BUS_FMT_UYVY8_1X16:
942  		color_format = 0x16;
943  		break;
944  	case MEDIA_BUS_FMT_UYVY10_1X20:
945  		color_format = 0x14;
946  		break;
947  	case MEDIA_BUS_FMT_UYVY12_1X24:
948  		color_format = 0x12;
949  		break;
950  
951  	default:
952  		return;
953  	}
954  
955  	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
956  		((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
957  		HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
958  	hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
959  
960  	/* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
961  	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
962  		HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
963  		HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
964  	hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
965  	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
966  	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
967  	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
968  	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
969  	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
970  	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
971  }
972  
is_color_space_conversion(struct dw_hdmi * hdmi)973  static int is_color_space_conversion(struct dw_hdmi *hdmi)
974  {
975  	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
976  	bool is_input_rgb, is_output_rgb;
977  
978  	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
979  	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
980  
981  	return (is_input_rgb != is_output_rgb) ||
982  	       (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
983  }
984  
is_color_space_decimation(struct dw_hdmi * hdmi)985  static int is_color_space_decimation(struct dw_hdmi *hdmi)
986  {
987  	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
988  		return 0;
989  
990  	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
991  	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
992  		return 1;
993  
994  	return 0;
995  }
996  
is_color_space_interpolation(struct dw_hdmi * hdmi)997  static int is_color_space_interpolation(struct dw_hdmi *hdmi)
998  {
999  	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1000  		return 0;
1001  
1002  	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1003  	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1004  		return 1;
1005  
1006  	return 0;
1007  }
1008  
is_csc_needed(struct dw_hdmi * hdmi)1009  static bool is_csc_needed(struct dw_hdmi *hdmi)
1010  {
1011  	return is_color_space_conversion(hdmi) ||
1012  	       is_color_space_decimation(hdmi) ||
1013  	       is_color_space_interpolation(hdmi);
1014  }
1015  
dw_hdmi_update_csc_coeffs(struct dw_hdmi * hdmi)1016  static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1017  {
1018  	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1019  	bool is_input_rgb, is_output_rgb;
1020  	unsigned i;
1021  	u32 csc_scale = 1;
1022  
1023  	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1024  	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1025  
1026  	if (!is_input_rgb && is_output_rgb) {
1027  		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1028  			csc_coeff = &csc_coeff_rgb_out_eitu601;
1029  		else
1030  			csc_coeff = &csc_coeff_rgb_out_eitu709;
1031  	} else if (is_input_rgb && !is_output_rgb) {
1032  		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1033  			csc_coeff = &csc_coeff_rgb_in_eitu601;
1034  		else
1035  			csc_coeff = &csc_coeff_rgb_in_eitu709;
1036  		csc_scale = 0;
1037  	} else if (is_input_rgb && is_output_rgb &&
1038  		   hdmi->hdmi_data.rgb_limited_range) {
1039  		csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1040  	}
1041  
1042  	/* The CSC registers are sequential, alternating MSB then LSB */
1043  	for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1044  		u16 coeff_a = (*csc_coeff)[0][i];
1045  		u16 coeff_b = (*csc_coeff)[1][i];
1046  		u16 coeff_c = (*csc_coeff)[2][i];
1047  
1048  		hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1049  		hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1050  		hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1051  		hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1052  		hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1053  		hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1054  	}
1055  
1056  	hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1057  		  HDMI_CSC_SCALE);
1058  }
1059  
hdmi_video_csc(struct dw_hdmi * hdmi)1060  static void hdmi_video_csc(struct dw_hdmi *hdmi)
1061  {
1062  	int color_depth = 0;
1063  	int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1064  	int decimation = 0;
1065  
1066  	/* YCC422 interpolation to 444 mode */
1067  	if (is_color_space_interpolation(hdmi))
1068  		interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1069  	else if (is_color_space_decimation(hdmi))
1070  		decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1071  
1072  	switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1073  	case 8:
1074  		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1075  		break;
1076  	case 10:
1077  		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1078  		break;
1079  	case 12:
1080  		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1081  		break;
1082  	case 16:
1083  		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1084  		break;
1085  
1086  	default:
1087  		return;
1088  	}
1089  
1090  	/* Configure the CSC registers */
1091  	hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1092  	hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1093  		  HDMI_CSC_SCALE);
1094  
1095  	dw_hdmi_update_csc_coeffs(hdmi);
1096  }
1097  
1098  /*
1099   * HDMI video packetizer is used to packetize the data.
1100   * for example, if input is YCC422 mode or repeater is used,
1101   * data should be repacked this module can be bypassed.
1102   */
hdmi_video_packetize(struct dw_hdmi * hdmi)1103  static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1104  {
1105  	unsigned int color_depth = 0;
1106  	unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1107  	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1108  	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1109  	u8 val, vp_conf;
1110  
1111  	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1112  	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1113  	    hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1114  		switch (hdmi_bus_fmt_color_depth(
1115  					hdmi->hdmi_data.enc_out_bus_format)) {
1116  		case 8:
1117  			color_depth = 4;
1118  			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1119  			break;
1120  		case 10:
1121  			color_depth = 5;
1122  			break;
1123  		case 12:
1124  			color_depth = 6;
1125  			break;
1126  		case 16:
1127  			color_depth = 7;
1128  			break;
1129  		default:
1130  			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1131  		}
1132  	} else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1133  		switch (hdmi_bus_fmt_color_depth(
1134  					hdmi->hdmi_data.enc_out_bus_format)) {
1135  		case 0:
1136  		case 8:
1137  			remap_size = HDMI_VP_REMAP_YCC422_16bit;
1138  			break;
1139  		case 10:
1140  			remap_size = HDMI_VP_REMAP_YCC422_20bit;
1141  			break;
1142  		case 12:
1143  			remap_size = HDMI_VP_REMAP_YCC422_24bit;
1144  			break;
1145  
1146  		default:
1147  			return;
1148  		}
1149  		output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1150  	} else {
1151  		return;
1152  	}
1153  
1154  	/* set the packetizer registers */
1155  	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1156  		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1157  		((hdmi_data->pix_repet_factor <<
1158  		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1159  		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1160  	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1161  
1162  	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1163  		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1164  
1165  	/* Data from pixel repeater block */
1166  	if (hdmi_data->pix_repet_factor > 1) {
1167  		vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1168  			  HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1169  	} else { /* data from packetizer block */
1170  		vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1171  			  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1172  	}
1173  
1174  	hdmi_modb(hdmi, vp_conf,
1175  		  HDMI_VP_CONF_PR_EN_MASK |
1176  		  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1177  
1178  	hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1179  		  HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1180  
1181  	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1182  
1183  	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1184  		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1185  			  HDMI_VP_CONF_PP_EN_ENABLE |
1186  			  HDMI_VP_CONF_YCC422_EN_DISABLE;
1187  	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1188  		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1189  			  HDMI_VP_CONF_PP_EN_DISABLE |
1190  			  HDMI_VP_CONF_YCC422_EN_ENABLE;
1191  	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1192  		vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1193  			  HDMI_VP_CONF_PP_EN_DISABLE |
1194  			  HDMI_VP_CONF_YCC422_EN_DISABLE;
1195  	} else {
1196  		return;
1197  	}
1198  
1199  	hdmi_modb(hdmi, vp_conf,
1200  		  HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1201  		  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1202  
1203  	hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1204  			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1205  		  HDMI_VP_STUFF_PP_STUFFING_MASK |
1206  		  HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1207  
1208  	hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1209  		  HDMI_VP_CONF);
1210  }
1211  
1212  /* -----------------------------------------------------------------------------
1213   * Synopsys PHY Handling
1214   */
1215  
hdmi_phy_test_clear(struct dw_hdmi * hdmi,unsigned char bit)1216  static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1217  				       unsigned char bit)
1218  {
1219  	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1220  		  HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1221  }
1222  
hdmi_phy_wait_i2c_done(struct dw_hdmi * hdmi,int msec)1223  static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1224  {
1225  	u32 val;
1226  
1227  	while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1228  		if (msec-- == 0)
1229  			return false;
1230  		udelay(1000);
1231  	}
1232  	hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1233  
1234  	return true;
1235  }
1236  
dw_hdmi_phy_i2c_write(struct dw_hdmi * hdmi,unsigned short data,unsigned char addr)1237  void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1238  			   unsigned char addr)
1239  {
1240  	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1241  	hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1242  	hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1243  		    HDMI_PHY_I2CM_DATAO_1_ADDR);
1244  	hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1245  		    HDMI_PHY_I2CM_DATAO_0_ADDR);
1246  	hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1247  		    HDMI_PHY_I2CM_OPERATION_ADDR);
1248  	hdmi_phy_wait_i2c_done(hdmi, 1000);
1249  }
1250  EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1251  
1252  /* Filter out invalid setups to avoid configuring SCDC and scrambling */
dw_hdmi_support_scdc(struct dw_hdmi * hdmi,const struct drm_display_info * display)1253  static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1254  				 const struct drm_display_info *display)
1255  {
1256  	/* Completely disable SCDC support for older controllers */
1257  	if (hdmi->version < 0x200a)
1258  		return false;
1259  
1260  	/* Disable if no DDC bus */
1261  	if (!hdmi->ddc)
1262  		return false;
1263  
1264  	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1265  	if (!display->hdmi.scdc.supported ||
1266  	    !display->hdmi.scdc.scrambling.supported)
1267  		return false;
1268  
1269  	/*
1270  	 * Disable if display only support low TMDS rates and scrambling
1271  	 * for low rates is not supported either
1272  	 */
1273  	if (!display->hdmi.scdc.scrambling.low_rates &&
1274  	    display->max_tmds_clock <= 340000)
1275  		return false;
1276  
1277  	return true;
1278  }
1279  
1280  /*
1281   * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1282   * - The Source shall suspend transmission of the TMDS clock and data
1283   * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1284   * from a 0 to a 1 or from a 1 to a 0
1285   * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1286   * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1287   * transmission of TMDS clock and data
1288   *
1289   * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1290   * helper should called right before enabling the TMDS Clock and Data in
1291   * the PHY configuration callback.
1292   */
dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi * hdmi,const struct drm_display_info * display)1293  void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1294  				       const struct drm_display_info *display)
1295  {
1296  	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1297  
1298  	/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1299  	if (dw_hdmi_support_scdc(hdmi, display)) {
1300  		if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1301  			drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1302  		else
1303  			drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1304  	}
1305  }
1306  EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1307  
dw_hdmi_phy_enable_powerdown(struct dw_hdmi * hdmi,bool enable)1308  static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1309  {
1310  	hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1311  			 HDMI_PHY_CONF0_PDZ_OFFSET,
1312  			 HDMI_PHY_CONF0_PDZ_MASK);
1313  }
1314  
dw_hdmi_phy_enable_tmds(struct dw_hdmi * hdmi,u8 enable)1315  static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1316  {
1317  	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1318  			 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1319  			 HDMI_PHY_CONF0_ENTMDS_MASK);
1320  }
1321  
dw_hdmi_phy_enable_svsret(struct dw_hdmi * hdmi,u8 enable)1322  static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1323  {
1324  	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1325  			 HDMI_PHY_CONF0_SVSRET_OFFSET,
1326  			 HDMI_PHY_CONF0_SVSRET_MASK);
1327  }
1328  
dw_hdmi_phy_gen2_pddq(struct dw_hdmi * hdmi,u8 enable)1329  void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1330  {
1331  	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1332  			 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1333  			 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1334  }
1335  EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1336  
dw_hdmi_phy_gen2_txpwron(struct dw_hdmi * hdmi,u8 enable)1337  void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1338  {
1339  	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1340  			 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1341  			 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1342  }
1343  EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1344  
dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi * hdmi,u8 enable)1345  static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1346  {
1347  	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1348  			 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1349  			 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1350  }
1351  
dw_hdmi_phy_sel_interface_control(struct dw_hdmi * hdmi,u8 enable)1352  static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1353  {
1354  	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1355  			 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1356  			 HDMI_PHY_CONF0_SELDIPIF_MASK);
1357  }
1358  
dw_hdmi_phy_reset(struct dw_hdmi * hdmi)1359  void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1360  {
1361  	/* PHY reset. The reset signal is active high on Gen2 PHYs. */
1362  	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1363  	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1364  }
1365  EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1366  
dw_hdmi_phy_i2c_set_addr(struct dw_hdmi * hdmi,u8 address)1367  void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1368  {
1369  	hdmi_phy_test_clear(hdmi, 1);
1370  	hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1371  	hdmi_phy_test_clear(hdmi, 0);
1372  }
1373  EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1374  
dw_hdmi_phy_power_off(struct dw_hdmi * hdmi)1375  static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1376  {
1377  	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1378  	unsigned int i;
1379  	u16 val;
1380  
1381  	if (phy->gen == 1) {
1382  		dw_hdmi_phy_enable_tmds(hdmi, 0);
1383  		dw_hdmi_phy_enable_powerdown(hdmi, true);
1384  		return;
1385  	}
1386  
1387  	dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1388  
1389  	/*
1390  	 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1391  	 * to low power mode.
1392  	 */
1393  	for (i = 0; i < 5; ++i) {
1394  		val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1395  		if (!(val & HDMI_PHY_TX_PHY_LOCK))
1396  			break;
1397  
1398  		usleep_range(1000, 2000);
1399  	}
1400  
1401  	if (val & HDMI_PHY_TX_PHY_LOCK)
1402  		dev_warn(hdmi->dev, "PHY failed to power down\n");
1403  	else
1404  		dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1405  
1406  	dw_hdmi_phy_gen2_pddq(hdmi, 1);
1407  }
1408  
dw_hdmi_phy_power_on(struct dw_hdmi * hdmi)1409  static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1410  {
1411  	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1412  	unsigned int i;
1413  	u8 val;
1414  
1415  	if (phy->gen == 1) {
1416  		dw_hdmi_phy_enable_powerdown(hdmi, false);
1417  
1418  		/* Toggle TMDS enable. */
1419  		dw_hdmi_phy_enable_tmds(hdmi, 0);
1420  		dw_hdmi_phy_enable_tmds(hdmi, 1);
1421  		return 0;
1422  	}
1423  
1424  	dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1425  	dw_hdmi_phy_gen2_pddq(hdmi, 0);
1426  
1427  	/* Wait for PHY PLL lock */
1428  	for (i = 0; i < 5; ++i) {
1429  		val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1430  		if (val)
1431  			break;
1432  
1433  		usleep_range(1000, 2000);
1434  	}
1435  
1436  	if (!val) {
1437  		dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1438  		return -ETIMEDOUT;
1439  	}
1440  
1441  	dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1442  	return 0;
1443  }
1444  
1445  /*
1446   * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1447   * information the DWC MHL PHY has the same register layout and is thus also
1448   * supported by this function.
1449   */
hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi * hdmi,const struct dw_hdmi_plat_data * pdata,unsigned long mpixelclock)1450  static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1451  		const struct dw_hdmi_plat_data *pdata,
1452  		unsigned long mpixelclock)
1453  {
1454  	const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1455  	const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1456  	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1457  
1458  	/* TOFIX Will need 420 specific PHY configuration tables */
1459  
1460  	/* PLL/MPLL Cfg - always match on final entry */
1461  	for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1462  		if (mpixelclock <= mpll_config->mpixelclock)
1463  			break;
1464  
1465  	for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1466  		if (mpixelclock <= curr_ctrl->mpixelclock)
1467  			break;
1468  
1469  	for (; phy_config->mpixelclock != ~0UL; phy_config++)
1470  		if (mpixelclock <= phy_config->mpixelclock)
1471  			break;
1472  
1473  	if (mpll_config->mpixelclock == ~0UL ||
1474  	    curr_ctrl->mpixelclock == ~0UL ||
1475  	    phy_config->mpixelclock == ~0UL)
1476  		return -EINVAL;
1477  
1478  	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1479  			      HDMI_3D_TX_PHY_CPCE_CTRL);
1480  	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1481  			      HDMI_3D_TX_PHY_GMPCTRL);
1482  	dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1483  			      HDMI_3D_TX_PHY_CURRCTRL);
1484  
1485  	dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1486  	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1487  			      HDMI_3D_TX_PHY_MSM_CTRL);
1488  
1489  	dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1490  	dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1491  			      HDMI_3D_TX_PHY_CKSYMTXCTRL);
1492  	dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1493  			      HDMI_3D_TX_PHY_VLEVCTRL);
1494  
1495  	/* Override and disable clock termination. */
1496  	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1497  			      HDMI_3D_TX_PHY_CKCALCTRL);
1498  
1499  	return 0;
1500  }
1501  
hdmi_phy_configure(struct dw_hdmi * hdmi,const struct drm_display_info * display)1502  static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1503  			      const struct drm_display_info *display)
1504  {
1505  	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1506  	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1507  	unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1508  	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1509  	int ret;
1510  
1511  	dw_hdmi_phy_power_off(hdmi);
1512  
1513  	dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1514  
1515  	/* Leave low power consumption mode by asserting SVSRET. */
1516  	if (phy->has_svsret)
1517  		dw_hdmi_phy_enable_svsret(hdmi, 1);
1518  
1519  	dw_hdmi_phy_reset(hdmi);
1520  
1521  	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1522  
1523  	dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1524  
1525  	/* Write to the PHY as configured by the platform */
1526  	if (pdata->configure_phy)
1527  		ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1528  	else
1529  		ret = phy->configure(hdmi, pdata, mpixelclock);
1530  	if (ret) {
1531  		dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1532  			mpixelclock);
1533  		return ret;
1534  	}
1535  
1536  	/* Wait for resuming transmission of TMDS clock and data */
1537  	if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1538  		msleep(100);
1539  
1540  	return dw_hdmi_phy_power_on(hdmi);
1541  }
1542  
dw_hdmi_phy_init(struct dw_hdmi * hdmi,void * data,const struct drm_display_info * display,const struct drm_display_mode * mode)1543  static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1544  			    const struct drm_display_info *display,
1545  			    const struct drm_display_mode *mode)
1546  {
1547  	int i, ret;
1548  
1549  	/* HDMI Phy spec says to do the phy initialization sequence twice */
1550  	for (i = 0; i < 2; i++) {
1551  		dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1552  		dw_hdmi_phy_sel_interface_control(hdmi, 0);
1553  
1554  		ret = hdmi_phy_configure(hdmi, display);
1555  		if (ret)
1556  			return ret;
1557  	}
1558  
1559  	return 0;
1560  }
1561  
dw_hdmi_phy_disable(struct dw_hdmi * hdmi,void * data)1562  static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1563  {
1564  	dw_hdmi_phy_power_off(hdmi);
1565  }
1566  
dw_hdmi_phy_read_hpd(struct dw_hdmi * hdmi,void * data)1567  enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1568  					       void *data)
1569  {
1570  	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1571  		connector_status_connected : connector_status_disconnected;
1572  }
1573  EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1574  
dw_hdmi_phy_update_hpd(struct dw_hdmi * hdmi,void * data,bool force,bool disabled,bool rxsense)1575  void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1576  			    bool force, bool disabled, bool rxsense)
1577  {
1578  	u8 old_mask = hdmi->phy_mask;
1579  
1580  	if (force || disabled || !rxsense)
1581  		hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1582  	else
1583  		hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1584  
1585  	if (old_mask != hdmi->phy_mask)
1586  		hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1587  }
1588  EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1589  
dw_hdmi_phy_setup_hpd(struct dw_hdmi * hdmi,void * data)1590  void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1591  {
1592  	/*
1593  	 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1594  	 * any pending interrupt.
1595  	 */
1596  	hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1597  	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1598  		    HDMI_IH_PHY_STAT0);
1599  
1600  	/* Enable cable hot plug irq. */
1601  	hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1602  
1603  	/* Clear and unmute interrupts. */
1604  	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1605  		    HDMI_IH_PHY_STAT0);
1606  	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1607  		    HDMI_IH_MUTE_PHY_STAT0);
1608  }
1609  EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1610  
1611  static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1612  	.init = dw_hdmi_phy_init,
1613  	.disable = dw_hdmi_phy_disable,
1614  	.read_hpd = dw_hdmi_phy_read_hpd,
1615  	.update_hpd = dw_hdmi_phy_update_hpd,
1616  	.setup_hpd = dw_hdmi_phy_setup_hpd,
1617  };
1618  
1619  /* -----------------------------------------------------------------------------
1620   * HDMI TX Setup
1621   */
1622  
hdmi_tx_hdcp_config(struct dw_hdmi * hdmi)1623  static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1624  {
1625  	u8 de;
1626  
1627  	if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1628  		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1629  	else
1630  		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1631  
1632  	/* disable rx detect */
1633  	hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1634  		  HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1635  
1636  	hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1637  
1638  	hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1639  		  HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1640  }
1641  
hdmi_config_AVI(struct dw_hdmi * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1642  static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1643  			    const struct drm_connector *connector,
1644  			    const struct drm_display_mode *mode)
1645  {
1646  	struct hdmi_avi_infoframe frame;
1647  	u8 val;
1648  
1649  	/* Initialise info frame from DRM mode */
1650  	drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1651  
1652  	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1653  		drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
1654  						   hdmi->hdmi_data.rgb_limited_range ?
1655  						   HDMI_QUANTIZATION_RANGE_LIMITED :
1656  						   HDMI_QUANTIZATION_RANGE_FULL);
1657  	} else {
1658  		frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1659  		frame.ycc_quantization_range =
1660  			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1661  	}
1662  
1663  	if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1664  		frame.colorspace = HDMI_COLORSPACE_YUV444;
1665  	else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1666  		frame.colorspace = HDMI_COLORSPACE_YUV422;
1667  	else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1668  		frame.colorspace = HDMI_COLORSPACE_YUV420;
1669  	else
1670  		frame.colorspace = HDMI_COLORSPACE_RGB;
1671  
1672  	/* Set up colorimetry */
1673  	if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1674  		switch (hdmi->hdmi_data.enc_out_encoding) {
1675  		case V4L2_YCBCR_ENC_601:
1676  			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1677  				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1678  			else
1679  				frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1680  			frame.extended_colorimetry =
1681  					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1682  			break;
1683  		case V4L2_YCBCR_ENC_709:
1684  			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1685  				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1686  			else
1687  				frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1688  			frame.extended_colorimetry =
1689  					HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1690  			break;
1691  		default: /* Carries no data */
1692  			frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1693  			frame.extended_colorimetry =
1694  					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1695  			break;
1696  		}
1697  	} else {
1698  		frame.colorimetry = HDMI_COLORIMETRY_NONE;
1699  		frame.extended_colorimetry =
1700  			HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1701  	}
1702  
1703  	/*
1704  	 * The Designware IP uses a different byte format from standard
1705  	 * AVI info frames, though generally the bits are in the correct
1706  	 * bytes.
1707  	 */
1708  
1709  	/*
1710  	 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1711  	 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1712  	 * bit 6 rather than 4.
1713  	 */
1714  	val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1715  	if (frame.active_aspect & 15)
1716  		val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1717  	if (frame.top_bar || frame.bottom_bar)
1718  		val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1719  	if (frame.left_bar || frame.right_bar)
1720  		val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1721  	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1722  
1723  	/* AVI data byte 2 differences: none */
1724  	val = ((frame.colorimetry & 0x3) << 6) |
1725  	      ((frame.picture_aspect & 0x3) << 4) |
1726  	      (frame.active_aspect & 0xf);
1727  	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1728  
1729  	/* AVI data byte 3 differences: none */
1730  	val = ((frame.extended_colorimetry & 0x7) << 4) |
1731  	      ((frame.quantization_range & 0x3) << 2) |
1732  	      (frame.nups & 0x3);
1733  	if (frame.itc)
1734  		val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1735  	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1736  
1737  	/* AVI data byte 4 differences: none */
1738  	val = frame.video_code & 0x7f;
1739  	hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1740  
1741  	/* AVI Data Byte 5- set up input and output pixel repetition */
1742  	val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1743  		HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1744  		HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1745  		((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1746  		HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1747  		HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1748  	hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1749  
1750  	/*
1751  	 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1752  	 * ycc range in bits 2,3 rather than 6,7
1753  	 */
1754  	val = ((frame.ycc_quantization_range & 0x3) << 2) |
1755  	      (frame.content_type & 0x3);
1756  	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1757  
1758  	/* AVI Data Bytes 6-13 */
1759  	hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1760  	hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1761  	hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1762  	hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1763  	hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1764  	hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1765  	hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1766  	hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1767  }
1768  
hdmi_config_vendor_specific_infoframe(struct dw_hdmi * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1769  static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1770  						  const struct drm_connector *connector,
1771  						  const struct drm_display_mode *mode)
1772  {
1773  	struct hdmi_vendor_infoframe frame;
1774  	u8 buffer[10];
1775  	ssize_t err;
1776  
1777  	err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector,
1778  							  mode);
1779  	if (err < 0)
1780  		/*
1781  		 * Going into that statement does not means vendor infoframe
1782  		 * fails. It just informed us that vendor infoframe is not
1783  		 * needed for the selected mode. Only 4k or stereoscopic 3D
1784  		 * mode requires vendor infoframe. So just simply return.
1785  		 */
1786  		return;
1787  
1788  	err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1789  	if (err < 0) {
1790  		dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1791  			err);
1792  		return;
1793  	}
1794  	hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1795  			HDMI_FC_DATAUTO0_VSD_MASK);
1796  
1797  	/* Set the length of HDMI vendor specific InfoFrame payload */
1798  	hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1799  
1800  	/* Set 24bit IEEE Registration Identifier */
1801  	hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1802  	hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1803  	hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1804  
1805  	/* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1806  	hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1807  	hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1808  
1809  	if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1810  		hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1811  
1812  	/* Packet frame interpolation */
1813  	hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1814  
1815  	/* Auto packets per frame and line spacing */
1816  	hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1817  
1818  	/* Configures the Frame Composer On RDRB mode */
1819  	hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1820  			HDMI_FC_DATAUTO0_VSD_MASK);
1821  }
1822  
hdmi_config_drm_infoframe(struct dw_hdmi * hdmi,const struct drm_connector * connector)1823  static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
1824  				      const struct drm_connector *connector)
1825  {
1826  	const struct drm_connector_state *conn_state = connector->state;
1827  	struct hdmi_drm_infoframe frame;
1828  	u8 buffer[30];
1829  	ssize_t err;
1830  	int i;
1831  
1832  	if (!hdmi->plat_data->use_drm_infoframe)
1833  		return;
1834  
1835  	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1836  		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1837  
1838  	err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1839  	if (err < 0)
1840  		return;
1841  
1842  	err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1843  	if (err < 0) {
1844  		dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1845  		return;
1846  	}
1847  
1848  	hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1849  	hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1850  
1851  	for (i = 0; i < frame.length; i++)
1852  		hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1853  
1854  	hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1855  	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1856  		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1857  }
1858  
hdmi_av_composer(struct dw_hdmi * hdmi,const struct drm_display_info * display,const struct drm_display_mode * mode)1859  static void hdmi_av_composer(struct dw_hdmi *hdmi,
1860  			     const struct drm_display_info *display,
1861  			     const struct drm_display_mode *mode)
1862  {
1863  	u8 inv_val, bytes;
1864  	const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1865  	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1866  	int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1867  	unsigned int vdisplay, hdisplay;
1868  
1869  	vmode->mpixelclock = mode->clock * 1000;
1870  
1871  	dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1872  
1873  	vmode->mtmdsclock = vmode->mpixelclock;
1874  
1875  	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1876  		switch (hdmi_bus_fmt_color_depth(
1877  				hdmi->hdmi_data.enc_out_bus_format)) {
1878  		case 16:
1879  			vmode->mtmdsclock = vmode->mpixelclock * 2;
1880  			break;
1881  		case 12:
1882  			vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
1883  			break;
1884  		case 10:
1885  			vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
1886  			break;
1887  		}
1888  	}
1889  
1890  	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1891  		vmode->mtmdsclock /= 2;
1892  
1893  	dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
1894  
1895  	/* Set up HDMI_FC_INVIDCONF */
1896  	inv_val = (hdmi->hdmi_data.hdcp_enable ||
1897  		   (dw_hdmi_support_scdc(hdmi, display) &&
1898  		    (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1899  		     hdmi_info->scdc.scrambling.low_rates)) ?
1900  		HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1901  		HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1902  
1903  	inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1904  		HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1905  		HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1906  
1907  	inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1908  		HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1909  		HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1910  
1911  	inv_val |= (vmode->mdataenablepolarity ?
1912  		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1913  		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1914  
1915  	if (hdmi->vic == 39)
1916  		inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1917  	else
1918  		inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1919  			HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1920  			HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1921  
1922  	inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1923  		HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1924  		HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1925  
1926  	inv_val |= hdmi->sink_is_hdmi ?
1927  		HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1928  		HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1929  
1930  	hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1931  
1932  	hdisplay = mode->hdisplay;
1933  	hblank = mode->htotal - mode->hdisplay;
1934  	h_de_hs = mode->hsync_start - mode->hdisplay;
1935  	hsync_len = mode->hsync_end - mode->hsync_start;
1936  
1937  	/*
1938  	 * When we're setting a YCbCr420 mode, we need
1939  	 * to adjust the horizontal timing to suit.
1940  	 */
1941  	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1942  		hdisplay /= 2;
1943  		hblank /= 2;
1944  		h_de_hs /= 2;
1945  		hsync_len /= 2;
1946  	}
1947  
1948  	vdisplay = mode->vdisplay;
1949  	vblank = mode->vtotal - mode->vdisplay;
1950  	v_de_vs = mode->vsync_start - mode->vdisplay;
1951  	vsync_len = mode->vsync_end - mode->vsync_start;
1952  
1953  	/*
1954  	 * When we're setting an interlaced mode, we need
1955  	 * to adjust the vertical timing to suit.
1956  	 */
1957  	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1958  		vdisplay /= 2;
1959  		vblank /= 2;
1960  		v_de_vs /= 2;
1961  		vsync_len /= 2;
1962  	}
1963  
1964  	/* Scrambling Control */
1965  	if (dw_hdmi_support_scdc(hdmi, display)) {
1966  		if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1967  		    hdmi_info->scdc.scrambling.low_rates) {
1968  			/*
1969  			 * HDMI2.0 Specifies the following procedure:
1970  			 * After the Source Device has determined that
1971  			 * SCDC_Present is set (=1), the Source Device should
1972  			 * write the accurate Version of the Source Device
1973  			 * to the Source Version field in the SCDCS.
1974  			 * Source Devices compliant shall set the
1975  			 * Source Version = 1.
1976  			 */
1977  			drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1978  				       &bytes);
1979  			drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1980  				min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1981  
1982  			/* Enabled Scrambling in the Sink */
1983  			drm_scdc_set_scrambling(hdmi->ddc, 1);
1984  
1985  			/*
1986  			 * To activate the scrambler feature, you must ensure
1987  			 * that the quasi-static configuration bit
1988  			 * fc_invidconf.HDCP_keepout is set at configuration
1989  			 * time, before the required mc_swrstzreq.tmdsswrst_req
1990  			 * reset request is issued.
1991  			 */
1992  			hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1993  				    HDMI_MC_SWRSTZ);
1994  			hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1995  		} else {
1996  			hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1997  			hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1998  				    HDMI_MC_SWRSTZ);
1999  			drm_scdc_set_scrambling(hdmi->ddc, 0);
2000  		}
2001  	}
2002  
2003  	/* Set up horizontal active pixel width */
2004  	hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
2005  	hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
2006  
2007  	/* Set up vertical active lines */
2008  	hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2009  	hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2010  
2011  	/* Set up horizontal blanking pixel region width */
2012  	hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2013  	hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2014  
2015  	/* Set up vertical blanking pixel region width */
2016  	hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2017  
2018  	/* Set up HSYNC active edge delay width (in pixel clks) */
2019  	hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2020  	hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2021  
2022  	/* Set up VSYNC active edge delay (in lines) */
2023  	hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2024  
2025  	/* Set up HSYNC active pulse width (in pixel clks) */
2026  	hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2027  	hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2028  
2029  	/* Set up VSYNC active edge delay (in lines) */
2030  	hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2031  }
2032  
2033  /* HDMI Initialization Step B.4 */
dw_hdmi_enable_video_path(struct dw_hdmi * hdmi)2034  static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2035  {
2036  	/* control period minimum duration */
2037  	hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2038  	hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2039  	hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2040  
2041  	/* Set to fill TMDS data channels */
2042  	hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2043  	hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2044  	hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2045  
2046  	/* Enable pixel clock and tmds data path */
2047  	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2048  			   HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2049  			   HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2050  			   HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2051  			   HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2052  	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2053  	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2054  
2055  	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2056  	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2057  
2058  	/* Enable csc path */
2059  	if (is_csc_needed(hdmi)) {
2060  		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2061  		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2062  
2063  		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2064  			    HDMI_MC_FLOWCTRL);
2065  	} else {
2066  		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2067  		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2068  
2069  		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2070  			    HDMI_MC_FLOWCTRL);
2071  	}
2072  }
2073  
2074  /* Workaround to clear the overflow condition */
dw_hdmi_clear_overflow(struct dw_hdmi * hdmi)2075  static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2076  {
2077  	unsigned int count;
2078  	unsigned int i;
2079  	u8 val;
2080  
2081  	/*
2082  	 * Under some circumstances the Frame Composer arithmetic unit can miss
2083  	 * an FC register write due to being busy processing the previous one.
2084  	 * The issue can be worked around by issuing a TMDS software reset and
2085  	 * then write one of the FC registers several times.
2086  	 *
2087  	 * The number of iterations matters and depends on the HDMI TX revision
2088  	 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
2089  	 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
2090  	 * as needing the workaround, with 4 iterations for v1.30a and 1
2091  	 * iteration for others.
2092  	 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2093  	 * the workaround with a single iteration.
2094  	 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2095  	 * been identified as needing the workaround with a single iteration.
2096  	 */
2097  
2098  	switch (hdmi->version) {
2099  	case 0x130a:
2100  		count = 4;
2101  		break;
2102  	case 0x131a:
2103  	case 0x132a:
2104  	case 0x200a:
2105  	case 0x201a:
2106  	case 0x211a:
2107  	case 0x212a:
2108  		count = 1;
2109  		break;
2110  	default:
2111  		return;
2112  	}
2113  
2114  	/* TMDS software reset */
2115  	hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2116  
2117  	val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2118  	for (i = 0; i < count; i++)
2119  		hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2120  }
2121  
hdmi_disable_overflow_interrupts(struct dw_hdmi * hdmi)2122  static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2123  {
2124  	hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2125  		    HDMI_IH_MUTE_FC_STAT2);
2126  }
2127  
dw_hdmi_setup(struct dw_hdmi * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)2128  static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2129  			 const struct drm_connector *connector,
2130  			 const struct drm_display_mode *mode)
2131  {
2132  	int ret;
2133  
2134  	hdmi_disable_overflow_interrupts(hdmi);
2135  
2136  	hdmi->vic = drm_match_cea_mode(mode);
2137  
2138  	if (!hdmi->vic) {
2139  		dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2140  	} else {
2141  		dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2142  	}
2143  
2144  	if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2145  	    (hdmi->vic == 21) || (hdmi->vic == 22) ||
2146  	    (hdmi->vic == 2) || (hdmi->vic == 3) ||
2147  	    (hdmi->vic == 17) || (hdmi->vic == 18))
2148  		hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2149  	else
2150  		hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2151  
2152  	hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2153  	hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2154  
2155  	if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2156  		hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2157  
2158  	/* TOFIX: Get input encoding from plat data or fallback to none */
2159  	if (hdmi->plat_data->input_bus_encoding)
2160  		hdmi->hdmi_data.enc_in_encoding =
2161  			hdmi->plat_data->input_bus_encoding;
2162  	else
2163  		hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2164  
2165  	if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2166  		hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2167  
2168  	hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2169  		drm_default_rgb_quant_range(mode) ==
2170  		HDMI_QUANTIZATION_RANGE_LIMITED;
2171  
2172  	hdmi->hdmi_data.pix_repet_factor = 0;
2173  	hdmi->hdmi_data.hdcp_enable = 0;
2174  	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2175  
2176  	/* HDMI Initialization Step B.1 */
2177  	hdmi_av_composer(hdmi, &connector->display_info, mode);
2178  
2179  	/* HDMI Initializateion Step B.2 */
2180  	ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2181  				  &connector->display_info,
2182  				  &hdmi->previous_mode);
2183  	if (ret)
2184  		return ret;
2185  	hdmi->phy.enabled = true;
2186  
2187  	/* HDMI Initialization Step B.3 */
2188  	dw_hdmi_enable_video_path(hdmi);
2189  
2190  	if (hdmi->sink_has_audio) {
2191  		dev_dbg(hdmi->dev, "sink has audio support\n");
2192  
2193  		/* HDMI Initialization Step E - Configure audio */
2194  		hdmi_clk_regenerator_update_pixel_clock(hdmi);
2195  		hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2196  	}
2197  
2198  	/* not for DVI mode */
2199  	if (hdmi->sink_is_hdmi) {
2200  		dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2201  
2202  		/* HDMI Initialization Step F - Configure AVI InfoFrame */
2203  		hdmi_config_AVI(hdmi, connector, mode);
2204  		hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2205  		hdmi_config_drm_infoframe(hdmi, connector);
2206  	} else {
2207  		dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2208  	}
2209  
2210  	hdmi_video_packetize(hdmi);
2211  	hdmi_video_csc(hdmi);
2212  	hdmi_video_sample(hdmi);
2213  	hdmi_tx_hdcp_config(hdmi);
2214  
2215  	dw_hdmi_clear_overflow(hdmi);
2216  
2217  	return 0;
2218  }
2219  
initialize_hdmi_ih_mutes(struct dw_hdmi * hdmi)2220  static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2221  {
2222  	u8 ih_mute;
2223  
2224  	/*
2225  	 * Boot up defaults are:
2226  	 * HDMI_IH_MUTE   = 0x03 (disabled)
2227  	 * HDMI_IH_MUTE_* = 0x00 (enabled)
2228  	 *
2229  	 * Disable top level interrupt bits in HDMI block
2230  	 */
2231  	ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2232  		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2233  		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2234  
2235  	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2236  
2237  	/* by default mask all interrupts */
2238  	hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2239  	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2240  	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2241  	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2242  	hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2243  	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2244  	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2245  	hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2246  	hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2247  	hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2248  	hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2249  	hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2250  	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2251  	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2252  
2253  	/* Disable interrupts in the IH_MUTE_* registers */
2254  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2255  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2256  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2257  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2258  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2259  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2260  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2261  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2262  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2263  	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2264  
2265  	/* Enable top level interrupt bits in HDMI block */
2266  	ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2267  		    HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2268  	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2269  }
2270  
dw_hdmi_poweron(struct dw_hdmi * hdmi)2271  static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2272  {
2273  	hdmi->bridge_is_on = true;
2274  
2275  	/*
2276  	 * The curr_conn field is guaranteed to be valid here, as this function
2277  	 * is only be called when !hdmi->disabled.
2278  	 */
2279  	dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2280  }
2281  
dw_hdmi_poweroff(struct dw_hdmi * hdmi)2282  static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2283  {
2284  	if (hdmi->phy.enabled) {
2285  		hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2286  		hdmi->phy.enabled = false;
2287  	}
2288  
2289  	hdmi->bridge_is_on = false;
2290  }
2291  
dw_hdmi_update_power(struct dw_hdmi * hdmi)2292  static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2293  {
2294  	int force = hdmi->force;
2295  
2296  	if (hdmi->disabled) {
2297  		force = DRM_FORCE_OFF;
2298  	} else if (force == DRM_FORCE_UNSPECIFIED) {
2299  		if (hdmi->rxsense)
2300  			force = DRM_FORCE_ON;
2301  		else
2302  			force = DRM_FORCE_OFF;
2303  	}
2304  
2305  	if (force == DRM_FORCE_OFF) {
2306  		if (hdmi->bridge_is_on)
2307  			dw_hdmi_poweroff(hdmi);
2308  	} else {
2309  		if (!hdmi->bridge_is_on)
2310  			dw_hdmi_poweron(hdmi);
2311  	}
2312  }
2313  
2314  /*
2315   * Adjust the detection of RXSENSE according to whether we have a forced
2316   * connection mode enabled, or whether we have been disabled.  There is
2317   * no point processing RXSENSE interrupts if we have a forced connection
2318   * state, or DRM has us disabled.
2319   *
2320   * We also disable rxsense interrupts when we think we're disconnected
2321   * to avoid floating TDMS signals giving false rxsense interrupts.
2322   *
2323   * Note: we still need to listen for HPD interrupts even when DRM has us
2324   * disabled so that we can detect a connect event.
2325   */
dw_hdmi_update_phy_mask(struct dw_hdmi * hdmi)2326  static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2327  {
2328  	if (hdmi->phy.ops->update_hpd)
2329  		hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2330  					  hdmi->force, hdmi->disabled,
2331  					  hdmi->rxsense);
2332  }
2333  
dw_hdmi_detect(struct dw_hdmi * hdmi)2334  static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2335  {
2336  	enum drm_connector_status result;
2337  
2338  	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2339  
2340  	mutex_lock(&hdmi->mutex);
2341  	if (result != hdmi->last_connector_result) {
2342  		dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2343  		handle_plugged_change(hdmi,
2344  				      result == connector_status_connected);
2345  		hdmi->last_connector_result = result;
2346  	}
2347  	mutex_unlock(&hdmi->mutex);
2348  
2349  	return result;
2350  }
2351  
dw_hdmi_get_edid(struct dw_hdmi * hdmi,struct drm_connector * connector)2352  static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
2353  				     struct drm_connector *connector)
2354  {
2355  	struct edid *edid;
2356  
2357  	if (!hdmi->ddc)
2358  		return NULL;
2359  
2360  	edid = drm_get_edid(connector, hdmi->ddc);
2361  	if (!edid) {
2362  		dev_dbg(hdmi->dev, "failed to get edid\n");
2363  		return NULL;
2364  	}
2365  
2366  	dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2367  		edid->width_cm, edid->height_cm);
2368  
2369  	hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2370  	hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2371  
2372  	return edid;
2373  }
2374  
2375  /* -----------------------------------------------------------------------------
2376   * DRM Connector Operations
2377   */
2378  
2379  static enum drm_connector_status
dw_hdmi_connector_detect(struct drm_connector * connector,bool force)2380  dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2381  {
2382  	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2383  					     connector);
2384  	return dw_hdmi_detect(hdmi);
2385  }
2386  
dw_hdmi_connector_get_modes(struct drm_connector * connector)2387  static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2388  {
2389  	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2390  					     connector);
2391  	struct edid *edid;
2392  	int ret;
2393  
2394  	edid = dw_hdmi_get_edid(hdmi, connector);
2395  	if (!edid)
2396  		return 0;
2397  
2398  	drm_connector_update_edid_property(connector, edid);
2399  	cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2400  	ret = drm_add_edid_modes(connector, edid);
2401  	kfree(edid);
2402  
2403  	return ret;
2404  }
2405  
hdr_metadata_equal(const struct drm_connector_state * old_state,const struct drm_connector_state * new_state)2406  static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
2407  			       const struct drm_connector_state *new_state)
2408  {
2409  	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
2410  	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
2411  
2412  	if (!old_blob || !new_blob)
2413  		return old_blob == new_blob;
2414  
2415  	if (old_blob->length != new_blob->length)
2416  		return false;
2417  
2418  	return !memcmp(old_blob->data, new_blob->data, old_blob->length);
2419  }
2420  
dw_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)2421  static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2422  					  struct drm_atomic_state *state)
2423  {
2424  	struct drm_connector_state *old_state =
2425  		drm_atomic_get_old_connector_state(state, connector);
2426  	struct drm_connector_state *new_state =
2427  		drm_atomic_get_new_connector_state(state, connector);
2428  	struct drm_crtc *crtc = new_state->crtc;
2429  	struct drm_crtc_state *crtc_state;
2430  
2431  	if (!crtc)
2432  		return 0;
2433  
2434  	if (!hdr_metadata_equal(old_state, new_state)) {
2435  		crtc_state = drm_atomic_get_crtc_state(state, crtc);
2436  		if (IS_ERR(crtc_state))
2437  			return PTR_ERR(crtc_state);
2438  
2439  		crtc_state->mode_changed = true;
2440  	}
2441  
2442  	return 0;
2443  }
2444  
dw_hdmi_connector_force(struct drm_connector * connector)2445  static void dw_hdmi_connector_force(struct drm_connector *connector)
2446  {
2447  	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2448  					     connector);
2449  
2450  	mutex_lock(&hdmi->mutex);
2451  	hdmi->force = connector->force;
2452  	dw_hdmi_update_power(hdmi);
2453  	dw_hdmi_update_phy_mask(hdmi);
2454  	mutex_unlock(&hdmi->mutex);
2455  }
2456  
2457  static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2458  	.fill_modes = drm_helper_probe_single_connector_modes,
2459  	.detect = dw_hdmi_connector_detect,
2460  	.destroy = drm_connector_cleanup,
2461  	.force = dw_hdmi_connector_force,
2462  	.reset = drm_atomic_helper_connector_reset,
2463  	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2464  	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2465  };
2466  
2467  static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2468  	.get_modes = dw_hdmi_connector_get_modes,
2469  	.atomic_check = dw_hdmi_connector_atomic_check,
2470  };
2471  
dw_hdmi_connector_create(struct dw_hdmi * hdmi)2472  static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
2473  {
2474  	struct drm_connector *connector = &hdmi->connector;
2475  	struct cec_connector_info conn_info;
2476  	struct cec_notifier *notifier;
2477  
2478  	if (hdmi->version >= 0x200a)
2479  		connector->ycbcr_420_allowed =
2480  			hdmi->plat_data->ycbcr_420_allowed;
2481  	else
2482  		connector->ycbcr_420_allowed = false;
2483  
2484  	connector->interlace_allowed = 1;
2485  	connector->polled = DRM_CONNECTOR_POLL_HPD;
2486  
2487  	drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2488  
2489  	drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2490  				    &dw_hdmi_connector_funcs,
2491  				    DRM_MODE_CONNECTOR_HDMIA,
2492  				    hdmi->ddc);
2493  
2494  	/*
2495  	 * drm_connector_attach_max_bpc_property() requires the
2496  	 * connector to have a state.
2497  	 */
2498  	drm_atomic_helper_connector_reset(connector);
2499  
2500  	drm_connector_attach_max_bpc_property(connector, 8, 16);
2501  
2502  	if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2503  		drm_object_attach_property(&connector->base,
2504  			connector->dev->mode_config.hdr_output_metadata_property, 0);
2505  
2506  	drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2507  
2508  	cec_fill_conn_info_from_drm(&conn_info, connector);
2509  
2510  	notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2511  	if (!notifier)
2512  		return -ENOMEM;
2513  
2514  	mutex_lock(&hdmi->cec_notifier_mutex);
2515  	hdmi->cec_notifier = notifier;
2516  	mutex_unlock(&hdmi->cec_notifier_mutex);
2517  
2518  	return 0;
2519  }
2520  
2521  /* -----------------------------------------------------------------------------
2522   * DRM Bridge Operations
2523   */
2524  
2525  /*
2526   * Possible output formats :
2527   * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2528   * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2529   * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2530   * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2531   * - MEDIA_BUS_FMT_YUV16_1X48,
2532   * - MEDIA_BUS_FMT_RGB161616_1X48,
2533   * - MEDIA_BUS_FMT_UYVY12_1X24,
2534   * - MEDIA_BUS_FMT_YUV12_1X36,
2535   * - MEDIA_BUS_FMT_RGB121212_1X36,
2536   * - MEDIA_BUS_FMT_UYVY10_1X20,
2537   * - MEDIA_BUS_FMT_YUV10_1X30,
2538   * - MEDIA_BUS_FMT_RGB101010_1X30,
2539   * - MEDIA_BUS_FMT_UYVY8_1X16,
2540   * - MEDIA_BUS_FMT_YUV8_1X24,
2541   * - MEDIA_BUS_FMT_RGB888_1X24,
2542   */
2543  
2544  /* Can return a maximum of 11 possible output formats for a mode/connector */
2545  #define MAX_OUTPUT_SEL_FORMATS	11
2546  
dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)2547  static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2548  					struct drm_bridge_state *bridge_state,
2549  					struct drm_crtc_state *crtc_state,
2550  					struct drm_connector_state *conn_state,
2551  					unsigned int *num_output_fmts)
2552  {
2553  	struct drm_connector *conn = conn_state->connector;
2554  	struct drm_display_info *info = &conn->display_info;
2555  	struct drm_display_mode *mode = &crtc_state->mode;
2556  	u8 max_bpc = conn_state->max_requested_bpc;
2557  	bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2558  			     (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
2559  	u32 *output_fmts;
2560  	unsigned int i = 0;
2561  
2562  	*num_output_fmts = 0;
2563  
2564  	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
2565  			      GFP_KERNEL);
2566  	if (!output_fmts)
2567  		return NULL;
2568  
2569  	/* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2570  	if (list_is_singular(&bridge->encoder->bridge_chain) ||
2571  	    list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
2572  		*num_output_fmts = 1;
2573  		output_fmts[0] = MEDIA_BUS_FMT_FIXED;
2574  
2575  		return output_fmts;
2576  	}
2577  
2578  	/*
2579  	 * If the current mode enforces 4:2:0, force the output but format
2580  	 * to 4:2:0 and do not add the YUV422/444/RGB formats
2581  	 */
2582  	if (conn->ycbcr_420_allowed &&
2583  	    (drm_mode_is_420_only(info, mode) ||
2584  	     (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
2585  
2586  		/* Order bus formats from 16bit to 8bit if supported */
2587  		if (max_bpc >= 16 && info->bpc == 16 &&
2588  		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2589  			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
2590  
2591  		if (max_bpc >= 12 && info->bpc >= 12 &&
2592  		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2593  			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
2594  
2595  		if (max_bpc >= 10 && info->bpc >= 10 &&
2596  		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2597  			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
2598  
2599  		/* Default 8bit fallback */
2600  		output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2601  
2602  		*num_output_fmts = i;
2603  
2604  		return output_fmts;
2605  	}
2606  
2607  	/*
2608  	 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
2609  	 * if supported. In any case the default RGB888 format is added
2610  	 */
2611  
2612  	/* Default 8bit RGB fallback */
2613  	output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2614  
2615  	if (max_bpc >= 16 && info->bpc == 16) {
2616  		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2617  			output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2618  
2619  		output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2620  	}
2621  
2622  	if (max_bpc >= 12 && info->bpc >= 12) {
2623  		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2624  			output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2625  
2626  		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2627  			output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2628  
2629  		output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2630  	}
2631  
2632  	if (max_bpc >= 10 && info->bpc >= 10) {
2633  		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2634  			output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2635  
2636  		if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2637  			output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2638  
2639  		output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2640  	}
2641  
2642  	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2643  		output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2644  
2645  	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2646  		output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2647  
2648  	*num_output_fmts = i;
2649  
2650  	return output_fmts;
2651  }
2652  
2653  /*
2654   * Possible input formats :
2655   * - MEDIA_BUS_FMT_RGB888_1X24
2656   * - MEDIA_BUS_FMT_YUV8_1X24
2657   * - MEDIA_BUS_FMT_UYVY8_1X16
2658   * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2659   * - MEDIA_BUS_FMT_RGB101010_1X30
2660   * - MEDIA_BUS_FMT_YUV10_1X30
2661   * - MEDIA_BUS_FMT_UYVY10_1X20
2662   * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2663   * - MEDIA_BUS_FMT_RGB121212_1X36
2664   * - MEDIA_BUS_FMT_YUV12_1X36
2665   * - MEDIA_BUS_FMT_UYVY12_1X24
2666   * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2667   * - MEDIA_BUS_FMT_RGB161616_1X48
2668   * - MEDIA_BUS_FMT_YUV16_1X48
2669   * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2670   */
2671  
2672  /* Can return a maximum of 3 possible input formats for an output format */
2673  #define MAX_INPUT_SEL_FORMATS	3
2674  
dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)2675  static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2676  					struct drm_bridge_state *bridge_state,
2677  					struct drm_crtc_state *crtc_state,
2678  					struct drm_connector_state *conn_state,
2679  					u32 output_fmt,
2680  					unsigned int *num_input_fmts)
2681  {
2682  	u32 *input_fmts;
2683  	unsigned int i = 0;
2684  
2685  	*num_input_fmts = 0;
2686  
2687  	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
2688  			     GFP_KERNEL);
2689  	if (!input_fmts)
2690  		return NULL;
2691  
2692  	switch (output_fmt) {
2693  	/* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
2694  	case MEDIA_BUS_FMT_FIXED:
2695  		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2696  		break;
2697  	/* 8bit */
2698  	case MEDIA_BUS_FMT_RGB888_1X24:
2699  		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2700  		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2701  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2702  		break;
2703  	case MEDIA_BUS_FMT_YUV8_1X24:
2704  		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2705  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2706  		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2707  		break;
2708  	case MEDIA_BUS_FMT_UYVY8_1X16:
2709  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2710  		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2711  		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2712  		break;
2713  
2714  	/* 10bit */
2715  	case MEDIA_BUS_FMT_RGB101010_1X30:
2716  		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2717  		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2718  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2719  		break;
2720  	case MEDIA_BUS_FMT_YUV10_1X30:
2721  		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2722  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2723  		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2724  		break;
2725  	case MEDIA_BUS_FMT_UYVY10_1X20:
2726  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2727  		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2728  		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2729  		break;
2730  
2731  	/* 12bit */
2732  	case MEDIA_BUS_FMT_RGB121212_1X36:
2733  		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2734  		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2735  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2736  		break;
2737  	case MEDIA_BUS_FMT_YUV12_1X36:
2738  		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2739  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2740  		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2741  		break;
2742  	case MEDIA_BUS_FMT_UYVY12_1X24:
2743  		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2744  		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2745  		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2746  		break;
2747  
2748  	/* 16bit */
2749  	case MEDIA_BUS_FMT_RGB161616_1X48:
2750  		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2751  		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2752  		break;
2753  	case MEDIA_BUS_FMT_YUV16_1X48:
2754  		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2755  		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2756  		break;
2757  
2758  	/*YUV 4:2:0 */
2759  	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2760  	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2761  	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
2762  	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
2763  		input_fmts[i++] = output_fmt;
2764  		break;
2765  	}
2766  
2767  	*num_input_fmts = i;
2768  
2769  	if (*num_input_fmts == 0) {
2770  		kfree(input_fmts);
2771  		input_fmts = NULL;
2772  	}
2773  
2774  	return input_fmts;
2775  }
2776  
dw_hdmi_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)2777  static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
2778  				       struct drm_bridge_state *bridge_state,
2779  				       struct drm_crtc_state *crtc_state,
2780  				       struct drm_connector_state *conn_state)
2781  {
2782  	struct dw_hdmi *hdmi = bridge->driver_private;
2783  
2784  	hdmi->hdmi_data.enc_out_bus_format =
2785  			bridge_state->output_bus_cfg.format;
2786  
2787  	hdmi->hdmi_data.enc_in_bus_format =
2788  			bridge_state->input_bus_cfg.format;
2789  
2790  	dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2791  		bridge_state->input_bus_cfg.format,
2792  		bridge_state->output_bus_cfg.format);
2793  
2794  	return 0;
2795  }
2796  
dw_hdmi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)2797  static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
2798  				 enum drm_bridge_attach_flags flags)
2799  {
2800  	struct dw_hdmi *hdmi = bridge->driver_private;
2801  
2802  	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
2803  		return 0;
2804  
2805  	return dw_hdmi_connector_create(hdmi);
2806  }
2807  
dw_hdmi_bridge_detach(struct drm_bridge * bridge)2808  static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2809  {
2810  	struct dw_hdmi *hdmi = bridge->driver_private;
2811  
2812  	mutex_lock(&hdmi->cec_notifier_mutex);
2813  	cec_notifier_conn_unregister(hdmi->cec_notifier);
2814  	hdmi->cec_notifier = NULL;
2815  	mutex_unlock(&hdmi->cec_notifier_mutex);
2816  }
2817  
2818  static enum drm_mode_status
dw_hdmi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)2819  dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2820  			  const struct drm_display_info *info,
2821  			  const struct drm_display_mode *mode)
2822  {
2823  	struct dw_hdmi *hdmi = bridge->driver_private;
2824  	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2825  	enum drm_mode_status mode_status = MODE_OK;
2826  
2827  	/* We don't support double-clocked modes */
2828  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2829  		return MODE_BAD;
2830  
2831  	if (pdata->mode_valid)
2832  		mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2833  						mode);
2834  
2835  	return mode_status;
2836  }
2837  
dw_hdmi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * mode)2838  static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2839  				    const struct drm_display_mode *orig_mode,
2840  				    const struct drm_display_mode *mode)
2841  {
2842  	struct dw_hdmi *hdmi = bridge->driver_private;
2843  
2844  	mutex_lock(&hdmi->mutex);
2845  
2846  	/* Store the display mode for plugin/DKMS poweron events */
2847  	memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2848  
2849  	mutex_unlock(&hdmi->mutex);
2850  }
2851  
dw_hdmi_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2852  static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
2853  					  struct drm_bridge_state *old_state)
2854  {
2855  	struct dw_hdmi *hdmi = bridge->driver_private;
2856  
2857  	mutex_lock(&hdmi->mutex);
2858  	hdmi->disabled = true;
2859  	hdmi->curr_conn = NULL;
2860  	dw_hdmi_update_power(hdmi);
2861  	dw_hdmi_update_phy_mask(hdmi);
2862  	mutex_unlock(&hdmi->mutex);
2863  }
2864  
dw_hdmi_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2865  static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
2866  					 struct drm_bridge_state *old_state)
2867  {
2868  	struct dw_hdmi *hdmi = bridge->driver_private;
2869  	struct drm_atomic_state *state = old_state->base.state;
2870  	struct drm_connector *connector;
2871  
2872  	connector = drm_atomic_get_new_connector_for_encoder(state,
2873  							     bridge->encoder);
2874  
2875  	mutex_lock(&hdmi->mutex);
2876  	hdmi->disabled = false;
2877  	hdmi->curr_conn = connector;
2878  	dw_hdmi_update_power(hdmi);
2879  	dw_hdmi_update_phy_mask(hdmi);
2880  	mutex_unlock(&hdmi->mutex);
2881  }
2882  
dw_hdmi_bridge_detect(struct drm_bridge * bridge)2883  static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
2884  {
2885  	struct dw_hdmi *hdmi = bridge->driver_private;
2886  
2887  	return dw_hdmi_detect(hdmi);
2888  }
2889  
dw_hdmi_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)2890  static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge,
2891  					    struct drm_connector *connector)
2892  {
2893  	struct dw_hdmi *hdmi = bridge->driver_private;
2894  
2895  	return dw_hdmi_get_edid(hdmi, connector);
2896  }
2897  
2898  static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2899  	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2900  	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2901  	.atomic_reset = drm_atomic_helper_bridge_reset,
2902  	.attach = dw_hdmi_bridge_attach,
2903  	.detach = dw_hdmi_bridge_detach,
2904  	.atomic_check = dw_hdmi_bridge_atomic_check,
2905  	.atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
2906  	.atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
2907  	.atomic_enable = dw_hdmi_bridge_atomic_enable,
2908  	.atomic_disable = dw_hdmi_bridge_atomic_disable,
2909  	.mode_set = dw_hdmi_bridge_mode_set,
2910  	.mode_valid = dw_hdmi_bridge_mode_valid,
2911  	.detect = dw_hdmi_bridge_detect,
2912  	.get_edid = dw_hdmi_bridge_get_edid,
2913  };
2914  
2915  /* -----------------------------------------------------------------------------
2916   * IRQ Handling
2917   */
2918  
dw_hdmi_i2c_irq(struct dw_hdmi * hdmi)2919  static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2920  {
2921  	struct dw_hdmi_i2c *i2c = hdmi->i2c;
2922  	unsigned int stat;
2923  
2924  	stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2925  	if (!stat)
2926  		return IRQ_NONE;
2927  
2928  	hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2929  
2930  	i2c->stat = stat;
2931  
2932  	complete(&i2c->cmp);
2933  
2934  	return IRQ_HANDLED;
2935  }
2936  
dw_hdmi_hardirq(int irq,void * dev_id)2937  static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2938  {
2939  	struct dw_hdmi *hdmi = dev_id;
2940  	u8 intr_stat;
2941  	irqreturn_t ret = IRQ_NONE;
2942  
2943  	if (hdmi->i2c)
2944  		ret = dw_hdmi_i2c_irq(hdmi);
2945  
2946  	intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2947  	if (intr_stat) {
2948  		hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2949  		return IRQ_WAKE_THREAD;
2950  	}
2951  
2952  	return ret;
2953  }
2954  
dw_hdmi_setup_rx_sense(struct dw_hdmi * hdmi,bool hpd,bool rx_sense)2955  void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2956  {
2957  	mutex_lock(&hdmi->mutex);
2958  
2959  	if (!hdmi->force) {
2960  		/*
2961  		 * If the RX sense status indicates we're disconnected,
2962  		 * clear the software rxsense status.
2963  		 */
2964  		if (!rx_sense)
2965  			hdmi->rxsense = false;
2966  
2967  		/*
2968  		 * Only set the software rxsense status when both
2969  		 * rxsense and hpd indicates we're connected.
2970  		 * This avoids what seems to be bad behaviour in
2971  		 * at least iMX6S versions of the phy.
2972  		 */
2973  		if (hpd)
2974  			hdmi->rxsense = true;
2975  
2976  		dw_hdmi_update_power(hdmi);
2977  		dw_hdmi_update_phy_mask(hdmi);
2978  	}
2979  	mutex_unlock(&hdmi->mutex);
2980  }
2981  EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2982  
dw_hdmi_irq(int irq,void * dev_id)2983  static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2984  {
2985  	struct dw_hdmi *hdmi = dev_id;
2986  	u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2987  	enum drm_connector_status status = connector_status_unknown;
2988  
2989  	intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2990  	phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2991  	phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2992  
2993  	phy_pol_mask = 0;
2994  	if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2995  		phy_pol_mask |= HDMI_PHY_HPD;
2996  	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2997  		phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2998  	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2999  		phy_pol_mask |= HDMI_PHY_RX_SENSE1;
3000  	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
3001  		phy_pol_mask |= HDMI_PHY_RX_SENSE2;
3002  	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
3003  		phy_pol_mask |= HDMI_PHY_RX_SENSE3;
3004  
3005  	if (phy_pol_mask)
3006  		hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
3007  
3008  	/*
3009  	 * RX sense tells us whether the TDMS transmitters are detecting
3010  	 * load - in other words, there's something listening on the
3011  	 * other end of the link.  Use this to decide whether we should
3012  	 * power on the phy as HPD may be toggled by the sink to merely
3013  	 * ask the source to re-read the EDID.
3014  	 */
3015  	if (intr_stat &
3016  	    (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
3017  		dw_hdmi_setup_rx_sense(hdmi,
3018  				       phy_stat & HDMI_PHY_HPD,
3019  				       phy_stat & HDMI_PHY_RX_SENSE);
3020  
3021  		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
3022  			mutex_lock(&hdmi->cec_notifier_mutex);
3023  			cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3024  			mutex_unlock(&hdmi->cec_notifier_mutex);
3025  		}
3026  
3027  		if (phy_stat & HDMI_PHY_HPD)
3028  			status = connector_status_connected;
3029  
3030  		if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE)))
3031  			status = connector_status_disconnected;
3032  	}
3033  
3034  	if (status != connector_status_unknown) {
3035  		dev_dbg(hdmi->dev, "EVENT=%s\n",
3036  			status == connector_status_connected ?
3037  			"plugin" : "plugout");
3038  
3039  		if (hdmi->bridge.dev) {
3040  			drm_helper_hpd_irq_event(hdmi->bridge.dev);
3041  			drm_bridge_hpd_notify(&hdmi->bridge, status);
3042  		}
3043  	}
3044  
3045  	hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3046  	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
3047  		    HDMI_IH_MUTE_PHY_STAT0);
3048  
3049  	return IRQ_HANDLED;
3050  }
3051  
3052  static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
3053  	{
3054  		.type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
3055  		.name = "DWC HDMI TX PHY",
3056  		.gen = 1,
3057  	}, {
3058  		.type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
3059  		.name = "DWC MHL PHY + HEAC PHY",
3060  		.gen = 2,
3061  		.has_svsret = true,
3062  		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3063  	}, {
3064  		.type = DW_HDMI_PHY_DWC_MHL_PHY,
3065  		.name = "DWC MHL PHY",
3066  		.gen = 2,
3067  		.has_svsret = true,
3068  		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3069  	}, {
3070  		.type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
3071  		.name = "DWC HDMI 3D TX PHY + HEAC PHY",
3072  		.gen = 2,
3073  		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3074  	}, {
3075  		.type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
3076  		.name = "DWC HDMI 3D TX PHY",
3077  		.gen = 2,
3078  		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3079  	}, {
3080  		.type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
3081  		.name = "DWC HDMI 2.0 TX PHY",
3082  		.gen = 2,
3083  		.has_svsret = true,
3084  		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3085  	}, {
3086  		.type = DW_HDMI_PHY_VENDOR_PHY,
3087  		.name = "Vendor PHY",
3088  	}
3089  };
3090  
dw_hdmi_detect_phy(struct dw_hdmi * hdmi)3091  static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3092  {
3093  	unsigned int i;
3094  	u8 phy_type;
3095  
3096  	phy_type = hdmi->plat_data->phy_force_vendor ?
3097  				DW_HDMI_PHY_VENDOR_PHY :
3098  				hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3099  
3100  	if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
3101  		/* Vendor PHYs require support from the glue layer. */
3102  		if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3103  			dev_err(hdmi->dev,
3104  				"Vendor HDMI PHY not supported by glue layer\n");
3105  			return -ENODEV;
3106  		}
3107  
3108  		hdmi->phy.ops = hdmi->plat_data->phy_ops;
3109  		hdmi->phy.data = hdmi->plat_data->phy_data;
3110  		hdmi->phy.name = hdmi->plat_data->phy_name;
3111  		return 0;
3112  	}
3113  
3114  	/* Synopsys PHYs are handled internally. */
3115  	for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
3116  		if (dw_hdmi_phys[i].type == phy_type) {
3117  			hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3118  			hdmi->phy.name = dw_hdmi_phys[i].name;
3119  			hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3120  
3121  			if (!dw_hdmi_phys[i].configure &&
3122  			    !hdmi->plat_data->configure_phy) {
3123  				dev_err(hdmi->dev, "%s requires platform support\n",
3124  					hdmi->phy.name);
3125  				return -ENODEV;
3126  			}
3127  
3128  			return 0;
3129  		}
3130  	}
3131  
3132  	dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3133  	return -ENODEV;
3134  }
3135  
dw_hdmi_cec_enable(struct dw_hdmi * hdmi)3136  static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3137  {
3138  	mutex_lock(&hdmi->mutex);
3139  	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3140  	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3141  	mutex_unlock(&hdmi->mutex);
3142  }
3143  
dw_hdmi_cec_disable(struct dw_hdmi * hdmi)3144  static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3145  {
3146  	mutex_lock(&hdmi->mutex);
3147  	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3148  	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3149  	mutex_unlock(&hdmi->mutex);
3150  }
3151  
3152  static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
3153  	.write = hdmi_writeb,
3154  	.read = hdmi_readb,
3155  	.enable = dw_hdmi_cec_enable,
3156  	.disable = dw_hdmi_cec_disable,
3157  };
3158  
3159  static const struct regmap_config hdmi_regmap_8bit_config = {
3160  	.reg_bits	= 32,
3161  	.val_bits	= 8,
3162  	.reg_stride	= 1,
3163  	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
3164  };
3165  
3166  static const struct regmap_config hdmi_regmap_32bit_config = {
3167  	.reg_bits	= 32,
3168  	.val_bits	= 32,
3169  	.reg_stride	= 4,
3170  	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
3171  };
3172  
dw_hdmi_init_hw(struct dw_hdmi * hdmi)3173  static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3174  {
3175  	initialize_hdmi_ih_mutes(hdmi);
3176  
3177  	/*
3178  	 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3179  	 * Even if we are using a separate i2c adapter doing this doesn't
3180  	 * hurt.
3181  	 */
3182  	dw_hdmi_i2c_init(hdmi);
3183  
3184  	if (hdmi->phy.ops->setup_hpd)
3185  		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3186  }
3187  
3188  /* -----------------------------------------------------------------------------
3189   * Probe/remove API, used from platforms based on the DRM bridge API.
3190   */
dw_hdmi_probe(struct platform_device * pdev,const struct dw_hdmi_plat_data * plat_data)3191  struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
3192  			      const struct dw_hdmi_plat_data *plat_data)
3193  {
3194  	struct device *dev = &pdev->dev;
3195  	struct device_node *np = dev->of_node;
3196  	struct platform_device_info pdevinfo;
3197  	struct device_node *ddc_node;
3198  	struct dw_hdmi_cec_data cec;
3199  	struct dw_hdmi *hdmi;
3200  	struct resource *iores = NULL;
3201  	int irq;
3202  	int ret;
3203  	u32 val = 1;
3204  	u8 prod_id0;
3205  	u8 prod_id1;
3206  	u8 config0;
3207  	u8 config3;
3208  
3209  	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
3210  	if (!hdmi)
3211  		return ERR_PTR(-ENOMEM);
3212  
3213  	hdmi->plat_data = plat_data;
3214  	hdmi->dev = dev;
3215  	hdmi->sample_rate = 48000;
3216  	hdmi->disabled = true;
3217  	hdmi->rxsense = true;
3218  	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3219  	hdmi->mc_clkdis = 0x7f;
3220  	hdmi->last_connector_result = connector_status_disconnected;
3221  
3222  	mutex_init(&hdmi->mutex);
3223  	mutex_init(&hdmi->audio_mutex);
3224  	mutex_init(&hdmi->cec_notifier_mutex);
3225  	spin_lock_init(&hdmi->audio_lock);
3226  
3227  	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3228  	if (ddc_node) {
3229  		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3230  		of_node_put(ddc_node);
3231  		if (!hdmi->ddc) {
3232  			dev_dbg(hdmi->dev, "failed to read ddc node\n");
3233  			return ERR_PTR(-EPROBE_DEFER);
3234  		}
3235  
3236  	} else {
3237  		dev_dbg(hdmi->dev, "no ddc property found\n");
3238  	}
3239  
3240  	if (!plat_data->regm) {
3241  		const struct regmap_config *reg_config;
3242  
3243  		of_property_read_u32(np, "reg-io-width", &val);
3244  		switch (val) {
3245  		case 4:
3246  			reg_config = &hdmi_regmap_32bit_config;
3247  			hdmi->reg_shift = 2;
3248  			break;
3249  		case 1:
3250  			reg_config = &hdmi_regmap_8bit_config;
3251  			break;
3252  		default:
3253  			dev_err(dev, "reg-io-width must be 1 or 4\n");
3254  			return ERR_PTR(-EINVAL);
3255  		}
3256  
3257  		iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3258  		hdmi->regs = devm_ioremap_resource(dev, iores);
3259  		if (IS_ERR(hdmi->regs)) {
3260  			ret = PTR_ERR(hdmi->regs);
3261  			goto err_res;
3262  		}
3263  
3264  		hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3265  		if (IS_ERR(hdmi->regm)) {
3266  			dev_err(dev, "Failed to configure regmap\n");
3267  			ret = PTR_ERR(hdmi->regm);
3268  			goto err_res;
3269  		}
3270  	} else {
3271  		hdmi->regm = plat_data->regm;
3272  	}
3273  
3274  	hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
3275  	if (IS_ERR(hdmi->isfr_clk)) {
3276  		ret = PTR_ERR(hdmi->isfr_clk);
3277  		dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3278  		goto err_res;
3279  	}
3280  
3281  	ret = clk_prepare_enable(hdmi->isfr_clk);
3282  	if (ret) {
3283  		dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
3284  		goto err_res;
3285  	}
3286  
3287  	hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
3288  	if (IS_ERR(hdmi->iahb_clk)) {
3289  		ret = PTR_ERR(hdmi->iahb_clk);
3290  		dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3291  		goto err_isfr;
3292  	}
3293  
3294  	ret = clk_prepare_enable(hdmi->iahb_clk);
3295  	if (ret) {
3296  		dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
3297  		goto err_isfr;
3298  	}
3299  
3300  	hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
3301  	if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
3302  		hdmi->cec_clk = NULL;
3303  	} else if (IS_ERR(hdmi->cec_clk)) {
3304  		ret = PTR_ERR(hdmi->cec_clk);
3305  		if (ret != -EPROBE_DEFER)
3306  			dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3307  				ret);
3308  
3309  		hdmi->cec_clk = NULL;
3310  		goto err_iahb;
3311  	} else {
3312  		ret = clk_prepare_enable(hdmi->cec_clk);
3313  		if (ret) {
3314  			dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
3315  				ret);
3316  			goto err_iahb;
3317  		}
3318  	}
3319  
3320  	/* Product and revision IDs */
3321  	hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3322  		      | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3323  	prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3324  	prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3325  
3326  	if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
3327  	    (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
3328  		dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3329  			hdmi->version, prod_id0, prod_id1);
3330  		ret = -ENODEV;
3331  		goto err_iahb;
3332  	}
3333  
3334  	ret = dw_hdmi_detect_phy(hdmi);
3335  	if (ret < 0)
3336  		goto err_iahb;
3337  
3338  	dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3339  		 hdmi->version >> 12, hdmi->version & 0xfff,
3340  		 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
3341  		 hdmi->phy.name);
3342  
3343  	dw_hdmi_init_hw(hdmi);
3344  
3345  	irq = platform_get_irq(pdev, 0);
3346  	if (irq < 0) {
3347  		ret = irq;
3348  		goto err_iahb;
3349  	}
3350  
3351  	ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
3352  					dw_hdmi_irq, IRQF_SHARED,
3353  					dev_name(dev), hdmi);
3354  	if (ret)
3355  		goto err_iahb;
3356  
3357  	/*
3358  	 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
3359  	 * N and cts values before enabling phy
3360  	 */
3361  	hdmi_init_clk_regenerator(hdmi);
3362  
3363  	/* If DDC bus is not specified, try to register HDMI I2C bus */
3364  	if (!hdmi->ddc) {
3365  		/* Look for (optional) stuff related to unwedging */
3366  		hdmi->pinctrl = devm_pinctrl_get(dev);
3367  		if (!IS_ERR(hdmi->pinctrl)) {
3368  			hdmi->unwedge_state =
3369  				pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3370  			hdmi->default_state =
3371  				pinctrl_lookup_state(hdmi->pinctrl, "default");
3372  
3373  			if (IS_ERR(hdmi->default_state) ||
3374  			    IS_ERR(hdmi->unwedge_state)) {
3375  				if (!IS_ERR(hdmi->unwedge_state))
3376  					dev_warn(dev,
3377  						 "Unwedge requires default pinctrl\n");
3378  				hdmi->default_state = NULL;
3379  				hdmi->unwedge_state = NULL;
3380  			}
3381  		}
3382  
3383  		hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3384  		if (IS_ERR(hdmi->ddc))
3385  			hdmi->ddc = NULL;
3386  	}
3387  
3388  	hdmi->bridge.driver_private = hdmi;
3389  	hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
3390  	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3391  			 | DRM_BRIDGE_OP_HPD;
3392  #ifdef CONFIG_OF
3393  	hdmi->bridge.of_node = pdev->dev.of_node;
3394  #endif
3395  
3396  	memset(&pdevinfo, 0, sizeof(pdevinfo));
3397  	pdevinfo.parent = dev;
3398  	pdevinfo.id = PLATFORM_DEVID_AUTO;
3399  
3400  	config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3401  	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3402  
3403  	if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
3404  		struct dw_hdmi_audio_data audio;
3405  
3406  		audio.phys = iores->start;
3407  		audio.base = hdmi->regs;
3408  		audio.irq = irq;
3409  		audio.hdmi = hdmi;
3410  		audio.get_eld = hdmi_audio_get_eld;
3411  		hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3412  		hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3413  
3414  		pdevinfo.name = "dw-hdmi-ahb-audio";
3415  		pdevinfo.data = &audio;
3416  		pdevinfo.size_data = sizeof(audio);
3417  		pdevinfo.dma_mask = DMA_BIT_MASK(32);
3418  		hdmi->audio = platform_device_register_full(&pdevinfo);
3419  	} else if (config0 & HDMI_CONFIG0_I2S) {
3420  		struct dw_hdmi_i2s_audio_data audio;
3421  
3422  		audio.hdmi	= hdmi;
3423  		audio.get_eld	= hdmi_audio_get_eld;
3424  		audio.write	= hdmi_writeb;
3425  		audio.read	= hdmi_readb;
3426  		hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3427  		hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3428  
3429  		pdevinfo.name = "dw-hdmi-i2s-audio";
3430  		pdevinfo.data = &audio;
3431  		pdevinfo.size_data = sizeof(audio);
3432  		pdevinfo.dma_mask = DMA_BIT_MASK(32);
3433  		hdmi->audio = platform_device_register_full(&pdevinfo);
3434  	}
3435  
3436  	if (config0 & HDMI_CONFIG0_CEC) {
3437  		cec.hdmi = hdmi;
3438  		cec.ops = &dw_hdmi_cec_ops;
3439  		cec.irq = irq;
3440  
3441  		pdevinfo.name = "dw-hdmi-cec";
3442  		pdevinfo.data = &cec;
3443  		pdevinfo.size_data = sizeof(cec);
3444  		pdevinfo.dma_mask = 0;
3445  
3446  		hdmi->cec = platform_device_register_full(&pdevinfo);
3447  	}
3448  
3449  	drm_bridge_add(&hdmi->bridge);
3450  
3451  	return hdmi;
3452  
3453  err_iahb:
3454  	clk_disable_unprepare(hdmi->iahb_clk);
3455  	if (hdmi->cec_clk)
3456  		clk_disable_unprepare(hdmi->cec_clk);
3457  err_isfr:
3458  	clk_disable_unprepare(hdmi->isfr_clk);
3459  err_res:
3460  	i2c_put_adapter(hdmi->ddc);
3461  
3462  	return ERR_PTR(ret);
3463  }
3464  EXPORT_SYMBOL_GPL(dw_hdmi_probe);
3465  
dw_hdmi_remove(struct dw_hdmi * hdmi)3466  void dw_hdmi_remove(struct dw_hdmi *hdmi)
3467  {
3468  	drm_bridge_remove(&hdmi->bridge);
3469  
3470  	if (hdmi->audio && !IS_ERR(hdmi->audio))
3471  		platform_device_unregister(hdmi->audio);
3472  	if (!IS_ERR(hdmi->cec))
3473  		platform_device_unregister(hdmi->cec);
3474  
3475  	/* Disable all interrupts */
3476  	hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3477  
3478  	clk_disable_unprepare(hdmi->iahb_clk);
3479  	clk_disable_unprepare(hdmi->isfr_clk);
3480  	if (hdmi->cec_clk)
3481  		clk_disable_unprepare(hdmi->cec_clk);
3482  
3483  	if (hdmi->i2c)
3484  		i2c_del_adapter(&hdmi->i2c->adap);
3485  	else
3486  		i2c_put_adapter(hdmi->ddc);
3487  }
3488  EXPORT_SYMBOL_GPL(dw_hdmi_remove);
3489  
3490  /* -----------------------------------------------------------------------------
3491   * Bind/unbind API, used from platforms based on the component framework.
3492   */
dw_hdmi_bind(struct platform_device * pdev,struct drm_encoder * encoder,const struct dw_hdmi_plat_data * plat_data)3493  struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
3494  			     struct drm_encoder *encoder,
3495  			     const struct dw_hdmi_plat_data *plat_data)
3496  {
3497  	struct dw_hdmi *hdmi;
3498  	int ret;
3499  
3500  	hdmi = dw_hdmi_probe(pdev, plat_data);
3501  	if (IS_ERR(hdmi))
3502  		return hdmi;
3503  
3504  	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3505  	if (ret) {
3506  		dw_hdmi_remove(hdmi);
3507  		DRM_ERROR("Failed to initialize bridge with drm\n");
3508  		return ERR_PTR(ret);
3509  	}
3510  
3511  	return hdmi;
3512  }
3513  EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3514  
dw_hdmi_unbind(struct dw_hdmi * hdmi)3515  void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3516  {
3517  	dw_hdmi_remove(hdmi);
3518  }
3519  EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3520  
dw_hdmi_resume(struct dw_hdmi * hdmi)3521  void dw_hdmi_resume(struct dw_hdmi *hdmi)
3522  {
3523  	dw_hdmi_init_hw(hdmi);
3524  }
3525  EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3526  
3527  MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3528  MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3529  MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3530  MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3531  MODULE_DESCRIPTION("DW HDMI transmitter driver");
3532  MODULE_LICENSE("GPL");
3533  MODULE_ALIAS("platform:dw-hdmi");
3534