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Searched refs:SF (Results 1 – 25 of 36) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mmhubbub.h143 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
144 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
145 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
146 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
147 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
148 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
149 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
150 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
151 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
152 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
[all …]
Ddcn30_optc.h112 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
113 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
114 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
115 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
116 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
117 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
118 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
119 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
120 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
121 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
Ddcn30_mpc.h292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
293 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
294 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
295 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
296 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
297 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
298 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
299 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
300 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
301 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mmhubbub.h98 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
99 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
100 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
101 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
102 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
103 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
104 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
105 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
106 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
107 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
[all …]
Ddcn20_dwb.h53 #define SF(reg_name, field_name, post_fix)\ macro
106 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
107 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
108 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
109 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
110 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
113 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
114 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
[all …]
Ddcn20_optc.h49 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
50 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
51 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
52 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
53 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
54 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
55 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
56 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
57 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
58 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
[all …]
Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
141 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
142 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
143 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
[all …]
Ddcn20_vmid.h47 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
48 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
49 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
50 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
51 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh)…
52 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh…
53 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
54 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.h49 #define SF(reg_name, field_name, post_fix)\ macro
87 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
88 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
89 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
91 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
92 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
93 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
94 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
95 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
[all …]
Ddcn10_optc.h186 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
187 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
188 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
189 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
190 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
191 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
192 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
193 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
194 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
195 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
[all …]
Ddcn10_mpc.h64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
71 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
49 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
[all …]
Ddce_mem_input.h248 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
249 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
276 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
277 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
322 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
323 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
324 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
325 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
326 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
330 SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
Ddce_hwseq.h476 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
518 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
526 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
527 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
528 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
529 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
530 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
/kernel/linux/linux-5.10/tools/lib/traceevent/plugins/
Dplugin_mac80211.c42 #define SF(fn) tep_print_num_field(s, fn ":%d", event, fn, record, 0) macro
58 SF("assoc"); SP(); in drv_bss_info_changed()
59 SF("aid"); SP(); in drv_bss_info_changed()
60 SF("cts"); SP(); in drv_bss_info_changed()
61 SF("shortpre"); SP(); in drv_bss_info_changed()
62 SF("shortslot"); SP(); in drv_bss_info_changed()
63 SF("dtimper"); SP(); in drv_bss_info_changed()
65 SF("bcnint"); SP(); in drv_bss_info_changed()
68 SF("enable_beacon"); in drv_bss_info_changed()
70 SF("ht_operation_mode"); in drv_bss_info_changed()
/kernel/linux/linux-5.10/fs/reiserfs/
Dprocfs.c50 #define SF( x ) ( r -> x ) macro
51 #define SFP( x ) SF( s_proc_info_data.x )
102 SF(s_mount_state) == REISERFS_VALID_FS ? in show_super()
118 SF(s_disk_reads), SF(s_disk_writes), SF(s_fix_nodes), in show_super()
119 SF(s_do_balance), SF(s_unneeded_left_neighbor), in show_super()
120 SF(s_good_search_by_key_reada), SF(s_bmaps), in show_super()
121 SF(s_bmaps_without_search), SF(s_direct2indirect), in show_super()
122 SF(s_indirect2direct), SFP(max_hash_collisions), SFP(breads), in show_super()
/kernel/linux/linux-5.10/scripts/selinux/
Dinstall_policy.sh9 SF=`which setfiles`
78 $SF -F file_contexts /
83 $SF -F file_contexts $mounts
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/
Depson,rtc7301.txt1 EPSON TOYOCOM RTC-7301SF/DG
/kernel/linux/linux-5.10/arch/x86/kernel/
Duprobes.c594 COND(78, 79, XF(SF)) \
597 COND(7c, 7d, XF(SF) != XF(OF)) \
598 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv50/
Dcrcc37d.c58 crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF); in crcc37d_set_src()
Dcrc907d.c53 crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SF(i)); in crc907d_set_src()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_factory_dcn21.c67 #define SF(reg_name, field_name, post_fix)\ macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_factory_dcn20.c69 #define SF(reg_name, field_name, post_fix)\ macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
Dhw_factory_dcn30.c77 #define SF(reg_name, field_name, post_fix)\ macro
/kernel/linux/linux-5.10/arch/s390/kernel/
Dperf_cpum_sf.c1989 CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC, PERF_EVENT_CPUM_SF);
1990 CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC_DIAG, PERF_EVENT_CPUM_SF_DIAG);
2015 [SF_CYCLES_BASIC_ATTR_IDX] = CPUMF_EVENT_PTR(SF, SF_CYCLES_BASIC)
2220 CPUMF_EVENT_PTR(SF, SF_CYCLES_BASIC_DIAG); in init_cpum_sampling_pmu()

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