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Searched refs:SMU_UCLK (Results 1 – 9 of 9) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c191 case SMU_UCLK: in renoir_get_dpm_clk_limited()
256 case SMU_UCLK: in renoir_get_dpm_ultimate_freq()
298 case SMU_UCLK: in renoir_get_dpm_ultimate_freq()
326 case SMU_UCLK: in renoir_get_dpm_ultimate_freq()
813 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); in renoir_set_peak_clock_by_device()
817 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); in renoir_set_peak_clock_by_device()
1035 ret = renoir_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); in renoir_read_sensor()
Dsmu_v12_0.c228 case SMU_UCLK: in smu_v12_0_set_soft_freq_limited_range()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c694 SMU_UCLK, in navi10_set_default_dpm_table()
956 case SMU_UCLK: in navi10_print_clk_levels()
1127 case SMU_UCLK: in navi10_force_clk_levels()
1261 case SMU_UCLK: in navi10_get_clock_by_type_with_latency()
1295 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); in navi10_pre_display_config_changed()
1298 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); in navi10_pre_display_config_changed()
1606 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
1739 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); in navi10_read_sensor()
1834 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); in navi10_display_disable_memory_clock_switch()
1836 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); in navi10_display_disable_memory_clock_switch()
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Dsmu_v11_0.c832 SMU_UCLK); in smu_v11_0_init_max_sustainable_clocks()
1036 clk_select = SMU_UCLK; in smu_v11_0_display_clock_voltage_request()
1047 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) in smu_v11_0_display_clock_voltage_request()
1052 if(clk_select == SMU_UCLK) in smu_v11_0_display_clock_voltage_request()
1591 case SMU_UCLK: in smu_v11_0_get_dpm_ultimate_freq()
Dsienna_cichlid_ppt.c627 SMU_UCLK, in sienna_cichlid_set_default_dpm_table()
953 case SMU_UCLK: in sienna_cichlid_print_clk_levels()
1051 case SMU_UCLK: in sienna_cichlid_force_clk_levels()
1124 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); in sienna_cichlid_pre_display_config_changed()
1127 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); in sienna_cichlid_pre_display_config_changed()
1437 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
1569 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); in sienna_cichlid_read_sensor()
1664 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); in sienna_cichlid_display_disable_memory_clock_switch()
1666 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); in sienna_cichlid_display_disable_memory_clock_switch()
Darcturus_ppt.c347 SMU_UCLK, in arcturus_set_default_dpm_table()
770 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); in arcturus_print_clk_levels()
1110 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); in arcturus_read_sensor()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dsmu_types.h196 SMU_UCLK, enumerator
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/
Dsmu_cmn.c299 case SMU_UCLK: in smu_cmn_clk_dpm_is_enabled()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/
Damdgpu_dpm.c934 ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK, in amdgpu_dpm_get_mclk()