1 /* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /** 33 * @defgroup Special Register Fields and Values 34 * @ingroup kernel 35 */ 36 37 #ifndef _ARCH_REGS_H 38 #define _ARCH_REGS_H 39 40 #ifdef __cplusplus 41 #if __cplusplus 42 extern "C" { 43 #endif /* __cplusplus */ 44 #endif /* __cplusplus */ 45 46 /* PS register -- imprecise exception */ 47 #define SPREG_PS_DEPC_SHIFT 4 48 #define SPREG_PS_DEPC_MASK 0x00000004 49 #define SPREG_PS_DEPC SPREG_PS_DEPC_MASK 50 /* PS register -- interrupt part */ 51 #define SPREG_PS_DI_SHIFT 3 52 #define SPREG_PS_DI_MASK 0x0000000F 53 #define SPREG_PS_DI SPREG_PS_DI_MASK 54 #define SPREG_PS_DI_DEPC 0x0000000C 55 /* PS register -- stack part */ 56 #define SPREG_PS_STACK_SHIFT 5 57 #define SPREG_PS_STACK_MASK 0x000000E0 58 #define SPREG_PS_STACK_INTERRUPT 0x00000000 59 #define SPREG_PS_STACK_CROSS 0x00000020 60 #define SPREG_PS_STACK_IDLE 0x00000040 61 #define SPREG_PS_STACK_KERNEL 0x00000060 62 #define SPREG_PS_STACK_PAGE 0x000000E0 63 #define SPREG_PS_STACK_FIRSTINT 0x00000080 64 #define SPREG_PS_STACK_FIRSTKER 0x000000A0 65 /* PS register -- entry no rotate */ 66 #define SPREG_PS_ENTRYNR_SHIFT 22 67 #define SPREG_PS_ENTRYNR_MASK 0x00400000 68 #define SPREG_PS_ENTRYNR SPREG_PS_ENTRYNR_MASK 69 70 /* Exccause Register -- cause */ 71 #define SPREG_EXCCAUSE_CAUSE_SHIFT 0 72 #define SPREG_EXCCAUSE_CAUSE_BITS 4 73 #define SPREG_EXCCAUSE_CAUSE_MASK 0x0000000F 74 75 /** 76 * @ingroup Execute level of core 77 */ 78 #define EXEC_LEVEL_APPLICATION_CODE 2 79 #define EXEC_LEVEL_EXCEPTION_HANDLER 3 80 #define EXEC_LEVEL_INTERRUPT_HANDLER 4 81 #define EXEC_LEVEL_NON_INTERRUPTIBLE 5 82 83 /** 84 * @ingroup Schedule Flag stored on Task Context 85 */ 86 #define OS_SCHED_FLAG_TASKPREEMT 4 /* Task Preemted through LOS_Schedule */ 87 88 /** 89 * @ingroup Context Fields Define 90 */ 91 #define CONTEXT_OFF_EPC 0 92 #define CONTEXT_OFF_PC 0 /* reuse with EPC */ 93 #define CONTEXT_OFF_PS 4 94 #define CONTEXT_OFF_A0 8 95 #define CONTEXT_OFF_A1 12 96 #define CONTEXT_OFF_A2 16 97 #define CONTEXT_OFF_A3 20 98 #define CONTEXT_OFF_A4 24 99 #define CONTEXT_OFF_A5 28 100 #define CONTEXT_OFF_A6 32 101 #define CONTEXT_OFF_A7 36 102 #define CONTEXT_OFF_A8 40 103 #define CONTEXT_OFF_A9 44 104 #define CONTEXT_OFF_A10 48 105 #define CONTEXT_OFF_A11 52 106 #define CONTEXT_OFF_A12 56 107 #define CONTEXT_OFF_A13 60 108 #define CONTEXT_OFF_A14 64 109 #define CONTEXT_OFF_A15 68 110 #define CONTEXT_OFF_RESERVED 72 111 #define CONTEXT_OFF_SAR 72 112 #define CONTEXT_OFF_SCHED_FLAG 76 /* reuse with exccause */ 113 #define CONTEXT_OFF_EXCCAUSE 76 114 #define CONTEXT_OFF_EXCVADDR 80 115 #define CONTEXT_OFF_LBEG 84 116 #define CONTEXT_OFF_LEND 88 117 #define CONTEXT_OFF_LCOUNT 92 118 119 #if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) 120 #define CONTEXT_OFF_TMP0 96 121 #define CONTEXT_OFF_CPENABLE 100 122 #define CONTEXT_OFF_CPSTORED 102 123 #define CONTEXT_OFF_FCR 104 124 #define CONTEXT_OFF_FSR 108 125 #define CONTEXT_OFF_F0 112 126 #define CONTEXT_OFF_F1 116 127 #define CONTEXT_OFF_F2 120 128 #define CONTEXT_OFF_F3 124 129 #define CONTEXT_OFF_F4 128 130 #define CONTEXT_OFF_F5 132 131 #define CONTEXT_OFF_F6 136 132 #define CONTEXT_OFF_F7 140 133 #define CONTEXT_OFF_F8 144 134 #define CONTEXT_OFF_F9 148 135 #define CONTEXT_OFF_F10 152 136 #define CONTEXT_OFF_F11 156 137 #define CONTEXT_OFF_F12 160 138 #define CONTEXT_OFF_F13 164 139 #define CONTEXT_OFF_F14 168 140 #define CONTEXT_OFF_F15 172 141 #define CONTEXT_SIZE 192 142 #else 143 #define CONTEXT_SIZE 112 144 #endif 145 #define LEVEL1_TINRERRUPT_CAUSE 4 146 #define ALLOC_CAUSE 5 147 #define LOWBIT_CALLNMODE 30 148 #define HIGHBIT_CALLNMODE 31 149 #define PS_OWB_SHIFT 8 150 #define EXCCAUSE_LEVEL1INTERRUPT 4 151 #define XTENSA_LOGREG_NUM 16 152 #define INDEX_OF_SP 1 153 #define INDEX_OF_ARGS0 6 154 155 #define WINDOWSTARTBITS 16 156 #define WINDOWBASEBITS 4 157 #define WINDOWSTARTMASK ((1 << WINDOWSTARTBITS) - 1) 158 159 #define WOE_ENABLE 0x40000 160 #define BIT_CALLINC 16 161 #define LEVEL_MASK 0xf 162 #define INT_MASK 5 163 #define LEVEL1_INT_MASK 1 164 #define USER_VECTOR_MODE 0x20 165 #define LEVEL1 1 166 #define LEVEL2 2 167 #define LEVEL3 3 168 #define LEVEL4 4 169 #define LEVEL5 5 170 171 #ifdef __cplusplus 172 #if __cplusplus 173 } 174 #endif /* __cplusplus */ 175 #endif /* __cplusplus */ 176 177 #endif /* _ARCH_REGS_H */ 178