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Searched refs:SSPP_VIG1 (Results 1 – 9 of 9) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
195 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
432 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
641 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
Dmdp5_ctl.c291 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
314 case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; in mdp_ctl_blend_ext_mask()
442 case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h70 SSPP_VIG1 = 2, enumerator
540 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); in __offset_PIPE()
Dmdp5_kms.c727 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c139 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; in dpu_hw_get_danger_status()
236 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c144 case SSPP_VIG1: in dpu_hw_ctl_get_bitmask_sspp()
395 case SSPP_VIG1: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h110 SSPP_VIG1, enumerator
Ddpu_hw_interrupts.c380 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
381 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
Ddpu_hw_catalog.c344 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,