Searched refs:UVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
D | uvd_v5_0.c | 659 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v5_0_set_sw_clock_gating() 660 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v5_0_set_sw_clock_gating()
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D | uvd_v6_0.c | 1319 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v6_0_set_sw_clock_gating() 1320 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v6_0_set_sw_clock_gating()
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D | uvd_v7_0.c | 1599 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1600 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
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D | sid.h | 1630 #define UVD_CGC_CTRL 0x3dc2 macro
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
D | si.c | 5176 tmp = RREG32(UVD_CGC_CTRL); in si_set_uvd_dcm() 5188 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm() 5199 u32 tmp = RREG32(UVD_CGC_CTRL); in si_init_uvd_internal_cg() 5201 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg() 5461 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg() 5464 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg() 5473 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg() 5476 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
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D | sid.h | 1568 #define UVD_CGC_CTRL 0xF4B0 macro
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D | cikd.h | 2085 #define UVD_CGC_CTRL 0xF4B0 macro
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D | cik.c | 6223 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg() 6226 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg() 6232 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg() 6235 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
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