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Searched refs:X86_CONFIG (Results 1 – 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/arch/x86/kernel/cpu/resctrl/
Dpseudo_lock.c1069 perf_miss_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1071 perf_hit_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1108 perf_hit_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
1110 perf_miss_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
/kernel/linux/linux-5.10/arch/x86/events/zhaoxin/
Dcore.c564 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
567 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
/kernel/linux/linux-5.10/arch/x86/events/intel/
Dcore.c3436 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3464 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
3488 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
3942 X86_CONFIG(.event=0xc0, .umask=0x01)) { in bdw_limit_period()
5073 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5076 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5231 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5234 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5271 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5274 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
[all …]
/kernel/linux/linux-5.10/arch/x86/events/
Dperf_event.h621 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value macro