Searched refs:XAXIDMA_TX_CR_OFFSET (Results 1 – 3 of 3) sorted by relevance
/kernel/linux/linux-5.10/drivers/net/ethernet/ni/ |
D | nixge.c | 26 #define XAXIDMA_TX_CR_OFFSET 0x00 /* Channel control */ macro 357 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init() 367 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_hw_dma_bd_init() 384 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init() 385 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, in nixge_hw_dma_bd_init() 416 __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET); in nixge_device_reset() 723 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_tx_irq() 727 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_tx_irq() 772 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_rx_irq() 776 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_rx_irq() [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/ |
D | xilinx_axienet_main.c | 313 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init() 323 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_dma_bd_init() 340 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init() 341 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, in axienet_dma_bd_init() 510 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK); in __axienet_device_reset() 514 XAXIDMA_TX_CR_OFFSET); in __axienet_device_reset() 971 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_tx_irq() 975 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_tx_irq() 1021 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_rx_irq() 1025 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_rx_irq() [all …]
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D | xilinx_axienet.h | 74 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ macro
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