| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/core/ |
| D | ramht.c | 27 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_hash() argument
36 hash ^= chid << (ramht->bits - 4); in nvkm_ramht_hash()
41 nvkm_ramht_search(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_search() argument
45 co = ho = nvkm_ramht_hash(ramht, chid, handle); in nvkm_ramht_search()
47 if (ramht->data[co].chid == chid) { in nvkm_ramht_search()
61 int chid, int addr, u32 handle, u32 context) in nvkm_ramht_update() argument
68 data->chid = chid; in nvkm_ramht_update()
75 data->chid = -1; in nvkm_ramht_update()
108 int chid, int addr, u32 handle, u32 context) in nvkm_ramht_insert() argument
112 if (nvkm_ramht_search(ramht, chid, handle)) in nvkm_ramht_insert()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | gp102.c | 31 gp102_disp_intr_error(struct nv50_disp *disp, int chid) in gp102_disp_intr_error() argument
35 u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12)); in gp102_disp_intr_error()
36 u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12)); in gp102_disp_intr_error()
37 u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12)); in gp102_disp_intr_error()
40 chid, (mthd & 0x0000ffc), data, mthd, unkn); in gp102_disp_intr_error()
42 if (chid < ARRAY_SIZE(disp->chan)) { in gp102_disp_intr_error()
45 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); in gp102_disp_intr_error()
52 nvkm_wr32(device, 0x61009c, (1 << chid)); in gp102_disp_intr_error()
53 nvkm_wr32(device, 0x6111f0 + (chid * 12), 0x90000000); in gp102_disp_intr_error()
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| D | dmacnv50.c | 36 struct nv50_disp *disp, int chid, int head, u64 push, in nv50_disp_dmac_new_() argument
44 ret = nv50_disp_chan_new_(func, mthd, disp, chid, chid, head, oclass, in nv50_disp_dmac_new_()
74 chan->chid.user, -10, handle, in nv50_disp_dmac_bind()
75 chan->chid.user << 28 | in nv50_disp_dmac_bind()
76 chan->chid.user); in nv50_disp_dmac_bind()
84 int ctrl = chan->chid.ctrl; in nv50_disp_dmac_fini()
85 int user = chan->chid.user; in nv50_disp_dmac_fini()
106 int ctrl = chan->chid.ctrl; in nv50_disp_dmac_init()
107 int user = chan->chid.user; in nv50_disp_dmac_init()
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| D | gf119.c | 90 gf119_disp_intr_error(struct nv50_disp *disp, int chid) in gf119_disp_intr_error() argument
94 u32 stat = nvkm_rd32(device, 0x6101f0 + (chid * 12)); in gf119_disp_intr_error()
97 u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12)); in gf119_disp_intr_error()
98 u32 code = nvkm_rd32(device, 0x6101f8 + (chid * 12)); in gf119_disp_intr_error()
104 chid, stat, type, reason ? reason->name : "", in gf119_disp_intr_error()
107 if (chid < ARRAY_SIZE(disp->chan)) { in gf119_disp_intr_error()
110 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); in gf119_disp_intr_error()
117 nvkm_wr32(device, 0x61009c, (1 << chid)); in gf119_disp_intr_error()
118 nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000); in gf119_disp_intr_error()
132 int chid = __ffs(stat); stat &= ~(1 << chid); in gf119_disp_intr() local
[all …]
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| D | dmacgv100.c | 31 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle()
45 chan->chid.user, -9, handle, in gv100_disp_dmac_bind()
46 chan->chid.user << 25 | 0x00000040); in gv100_disp_dmac_bind()
53 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_fini()
54 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_fini()
66 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_init()
67 const u32 poff = chan->chid.ctrl * 0x10; in gv100_disp_dmac_init()
68 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_init()
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| D | dmacgf119.c | 34 chan->chid.user, -9, handle, in gf119_disp_dmac_bind()
35 chan->chid.user << 27 | 0x00000001); in gf119_disp_dmac_bind()
43 int ctrl = chan->chid.ctrl; in gf119_disp_dmac_fini()
44 int user = chan->chid.user; in gf119_disp_dmac_fini()
65 int ctrl = chan->chid.ctrl; in gf119_disp_dmac_init()
66 int user = chan->chid.user; in gf119_disp_dmac_init()
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| D | channv50.c | 89 mthd->name, chan->chid.user); in nv50_disp_chan_mthd()
125 nv50_disp_chan_uevent_send(struct nv50_disp *disp, int chid) in nv50_disp_chan_uevent_send() argument
130 nvkm_event_send(&disp->uevent, 1, chid, &rep, sizeof(rep)); in nv50_disp_chan_uevent_send()
146 notify->index = chan->chid.user; in nv50_disp_chan_uevent_ctor()
164 return 0x640000 + (chan->chid.user * 0x1000); in nv50_disp_chan_user()
171 const u32 mask = 0x00010001 << chan->chid.user; in nv50_disp_chan_intr()
172 const u32 data = en ? 0x00010000 << chan->chid.user : 0x00000000; in nv50_disp_chan_intr()
319 if (chan->chid.user >= 0) in nv50_disp_chan_dtor()
320 disp->chan[chan->chid.user] = NULL; in nv50_disp_chan_dtor()
354 chan->chid.ctrl = ctrl; in nv50_disp_chan_new_()
[all …]
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| D | piocgf119.c | 35 int ctrl = chan->chid.ctrl; in gf119_disp_pioc_fini()
36 int user = chan->chid.user; in gf119_disp_pioc_fini()
54 int ctrl = chan->chid.ctrl; in gf119_disp_pioc_init()
55 int user = chan->chid.user; in gf119_disp_pioc_init()
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| D | piocnv50.c | 35 int ctrl = chan->chid.ctrl; in nv50_disp_pioc_fini()
36 int user = chan->chid.user; in nv50_disp_pioc_fini()
54 int ctrl = chan->chid.ctrl; in nv50_disp_pioc_init()
55 int user = chan->chid.user; in nv50_disp_pioc_init()
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| D | gv100.c | 97 gv100_disp_exception(struct nv50_disp *disp, int chid) in gv100_disp_exception() argument
101 u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); in gv100_disp_exception()
112 if (chid <= 32) { in gv100_disp_exception()
113 u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); in gv100_disp_exception()
114 u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); in gv100_disp_exception()
117 chid, stat, type, reason ? reason->name : "", in gv100_disp_exception()
122 chid, stat, type, reason ? reason->name : "", mthd); in gv100_disp_exception()
125 if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) { in gv100_disp_exception()
128 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); in gv100_disp_exception()
135 nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000); in gv100_disp_exception()
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| D | cursgv100.c | 30 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_curs_idle()
52 const u32 hoff = chan->chid.ctrl * 4; in gv100_disp_curs_fini()
63 nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001); in gv100_disp_curs_init()
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| D | channv50.h | 17 } chid; member
42 struct nv50_disp *, int chid, int head, u64 push,
77 struct nv50_disp *, int chid,
82 struct nv50_disp *, int chid,
87 struct nv50_disp *, int chid,
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | dmanv40.c | 68 int chid; in nv40_fifo_dma_engine_fini() local
76 chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); in nv40_fifo_dma_engine_fini()
77 if (chid == chan->base.chid) in nv40_fifo_dma_engine_fini()
98 int chid; in nv40_fifo_dma_engine_init() local
107 chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); in nv40_fifo_dma_engine_init()
108 if (chid == chan->base.chid) in nv40_fifo_dma_engine_init()
148 u32 context = chan->base.chid << 23; in nv40_fifo_dma_object_ctor()
163 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, in nv40_fifo_dma_object_ctor()
221 args->v0.chid = chan->base.chid; in nv40_fifo_dma_new()
222 chan->ramfc = chan->base.chid * 128; in nv40_fifo_dma_new()
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| D | nv04.c | 108 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) in nv04_fifo_swmthd() argument
127 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); in nv04_fifo_swmthd()
137 nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get) in nv04_fifo_cache_error() argument
163 !nv04_fifo_swmthd(device, chid, mthd, data)) { in nv04_fifo_cache_error()
164 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); in nv04_fifo_cache_error()
167 chid, chan ? chan->object.client->name : "unknown", in nv04_fifo_cache_error()
188 nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) in nv04_fifo_dma_pusher() argument
200 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); in nv04_fifo_dma_pusher()
211 chid, name, ho_get, dma_get, ho_put, dma_put, in nv04_fifo_dma_pusher()
226 chid, name, dma_get, dma_put, state, in nv04_fifo_dma_pusher()
[all …]
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| D | dmanv04.c | 52 u32 context = 0x80000000 | chan->base.chid << 24; in nv04_fifo_dma_object_ctor()
67 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, in nv04_fifo_dma_object_ctor()
84 u32 chid; in nv04_fifo_dma_fini() local
91 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask; in nv04_fifo_dma_fini()
92 if (chid == chan->base.chid) { in nv04_fifo_dma_fini()
121 nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); in nv04_fifo_dma_fini()
132 u32 mask = 1 << chan->base.chid; in nv04_fifo_dma_init()
202 args->v0.chid = chan->base.chid; in nv04_fifo_dma_new()
203 chan->ramfc = chan->base.chid * 32; in nv04_fifo_dma_new()
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| D | gpfifogk104.c | 50 nvkm_wr32(device, 0x002634, chan->base.chid); in gk104_fifo_gpfifo_kick_locked()
57 cgrp ? cgrp->id : chan->base.chid, client->name); in gk104_fifo_gpfifo_kick_locked()
58 nvkm_fifo_recover_chan(&fifo->base, chan->base.chid); in gk104_fifo_gpfifo_kick_locked()
189 u32 coff = chan->base.chid * 8; in gk104_fifo_gpfifo_fini()
208 u32 coff = chan->base.chid * 8; in gk104_fifo_gpfifo_init()
243 gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid, in gk104_fifo_gpfifo_new_() argument
282 *chid = chan->base.chid; in gk104_fifo_gpfifo_new_()
291 chan->cgrp->id = chan->base.chid; in gk104_fifo_gpfifo_new_()
298 usermem = chan->base.chid * 0x200; in gk104_fifo_gpfifo_new_()
321 nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid); in gk104_fifo_gpfifo_new_()
[all …]
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| D | channv50.c | 81 chan->base.chid, chan->base.object.client->name); in nv50_fifo_chan_engine_fini()
184 u32 chid = chan->base.chid; in nv50_fifo_chan_fini() local
187 nvkm_mask(device, 0x002600 + (chid * 4), 0x80000000, 0x00000000); in nv50_fifo_chan_fini()
189 nvkm_wr32(device, 0x002600 + (chid * 4), 0x00000000); in nv50_fifo_chan_fini()
199 u32 chid = chan->base.chid; in nv50_fifo_chan_init() local
201 nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | addr); in nv50_fifo_chan_init()
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| D | gpfifogf100.c | 81 nvkm_wr32(device, 0x002634, chan->base.chid); in gf100_fifo_gpfifo_engine_fini()
83 if (nvkm_rd32(device, 0x002634) == chan->base.chid) in gf100_fifo_gpfifo_engine_fini()
87 chan->base.chid, chan->base.object.client->name); in gf100_fifo_gpfifo_engine_fini()
164 u32 coff = chan->base.chid * 8; in gf100_fifo_gpfifo_fini()
184 u32 coff = chan->base.chid * 8; in gf100_fifo_gpfifo_init()
258 args->v0.chid = chan->base.chid; in gf100_fifo_gpfifo_new()
262 usermem = chan->base.chid * 0x1000; in gf100_fifo_gpfifo_new()
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| D | gpfifogv100.c | 34 return chan->chid; in gv100_fifo_gpfifo_submit_token()
124 struct gk104_fifo *fifo, u64 *runlists, u16 *chid, in gv100_fifo_gpfifo_new_() argument
161 *chid = chan->base.chid; in gv100_fifo_gpfifo_new_()
171 chan->cgrp->id = chan->base.chid; in gv100_fifo_gpfifo_new_()
178 usermem = chan->base.chid * 0x200; in gv100_fifo_gpfifo_new_()
213 nvkm_wo32(chan->base.inst, 0x0e8, chan->base.chid); in gv100_fifo_gpfifo_new_()
244 &args->v0.chid, in gv100_fifo_gpfifo_new()
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| D | base.c | 37 nvkm_fifo_recover_chan(struct nvkm_fifo *fifo, int chid) in nvkm_fifo_recover_chan() argument
43 fifo->func->recover_chan(fifo, chid); in nvkm_fifo_recover_chan()
105 nvkm_fifo_chan_chid(struct nvkm_fifo *fifo, int chid, unsigned long *rflags) in nvkm_fifo_chan_chid() argument
111 if (chan->chid == chid) { in nvkm_fifo_chan_chid()
123 nvkm_fifo_kevent(struct nvkm_fifo *fifo, int chid) in nvkm_fifo_kevent() argument
125 nvkm_event_send(&fifo->kevent, 1, chid, NULL, 0); in nvkm_fifo_kevent()
136 notify->index = chan->chid; in nvkm_fifo_kevent_ctor()
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| D | priv.h | 11 void nvkm_fifo_kevent(struct nvkm_fifo *, int chid);
12 void nvkm_fifo_recover_chan(struct nvkm_fifo *, int chid);
30 void (*recover_chan)(struct nvkm_fifo *, int chid);
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| D | gf100.c | 66 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); in gf100_fifo_runlist_commit()
181 u32 chid = chan->base.chid; in gf100_fifo_recover() local
184 nvkm_subdev_name[engine->subdev.index], chid); in gf100_fifo_recover()
187 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); in gf100_fifo_recover()
194 nvkm_fifo_kevent(&fifo->base, chid); in gf100_fifo_recover()
302 info->reason, er ? er->name : "", chan ? chan->chid : -1, in gf100_fifo_fault()
332 u32 chid = (stat & 0x0000007f); in gf100_fifo_intr_sched_ctxsw() local
337 if (chan->base.chid == chid) { in gf100_fifo_intr_sched_ctxsw()
412 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; in gf100_fifo_intr_pbdma() local
422 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) in gf100_fifo_intr_pbdma()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv20.c | 24 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); in nv20_gr_chan_init()
36 int chid = -1; in nv20_gr_chan_fini() local
40 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; in nv20_gr_chan_fini()
41 if (chan->chid == chid) { in nv20_gr_chan_fini()
54 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); in nv20_gr_chan_fini()
86 chan->chid = fifoch->chid; in nv20_gr_chan_new()
96 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv20_gr_chan_new()
190 u32 chid = (addr & 0x01f00000) >> 20; in nv20_gr_intr() local
199 chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags); in nv20_gr_intr()
211 show, msg, nsource, src, nstatus, sta, chid, in nv20_gr_intr()
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| D | nv10.c | 402 int chid; member
552 int chid = nvkm_rd32(device, 0x400148) >> 24; in nv10_gr_channel() local
553 if (chid < ARRAY_SIZE(gr->chan)) in nv10_gr_channel()
554 chan = gr->chan[chid]; in nv10_gr_channel()
812 nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) in nv10_gr_load_dma_vtxbuf() argument
861 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); in nv10_gr_load_dma_vtxbuf()
883 nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) in nv10_gr_load_context() argument
901 nv10_gr_load_dma_vtxbuf(chan, chid, inst); in nv10_gr_load_context()
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
937 int chid; in nv10_gr_context_switch() local
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| D | ramht.h | 9 int chid; member
26 int chid, int addr, u32 handle, u32 context);
29 nvkm_ramht_search(struct nvkm_ramht *, int chid, u32 handle);
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