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Searched refs:clk_regmap (Results 1 – 25 of 86) sorted by relevance

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/kernel/linux/linux-5.10/drivers/clk/meson/
Daxg-audio.c324 static struct clk_regmap ddr_arb =
326 static struct clk_regmap pdm =
328 static struct clk_regmap tdmin_a =
330 static struct clk_regmap tdmin_b =
332 static struct clk_regmap tdmin_c =
334 static struct clk_regmap tdmin_lb =
336 static struct clk_regmap tdmout_a =
338 static struct clk_regmap tdmout_b =
340 static struct clk_regmap tdmout_c =
342 static struct clk_regmap frddr_a =
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Dgxbb.c85 static struct clk_regmap gxbb_fixed_pll_dco = {
128 static struct clk_regmap gxbb_fixed_pll = {
162 static struct clk_regmap gxbb_hdmi_pll_dco = {
210 static struct clk_regmap gxl_hdmi_pll_dco = {
264 static struct clk_regmap gxbb_hdmi_pll_od = {
282 static struct clk_regmap gxbb_hdmi_pll_od2 = {
300 static struct clk_regmap gxbb_hdmi_pll = {
318 static struct clk_regmap gxl_hdmi_pll_od = {
336 static struct clk_regmap gxl_hdmi_pll_od2 = {
354 static struct clk_regmap gxl_hdmi_pll = {
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Dclk-phase.c16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase()
50 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_set_phase()
76 meson_clk_triphase_data(struct clk_regmap *clk) in meson_clk_triphase_data()
83 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_sync()
97 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_get_phase()
109 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_set_phase()
135 meson_sclk_ws_inv_data(struct clk_regmap *clk) in meson_sclk_ws_inv_data()
142 struct clk_regmap *clk = to_clk_regmap(hw); in meson_sclk_ws_inv_sync()
155 struct clk_regmap *clk = to_clk_regmap(hw); in meson_sclk_ws_inv_get_phase()
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Dg12a.c29 static struct clk_regmap g12a_fixed_pll_dco = {
72 static struct clk_regmap g12a_fixed_pll = {
98 static struct clk_regmap g12a_sys_pll_dco = {
139 static struct clk_regmap g12a_sys_pll = {
157 static struct clk_regmap g12b_sys1_pll_dco = {
198 static struct clk_regmap g12b_sys1_pll = {
216 static struct clk_regmap g12a_sys_pll_div16_en = {
233 static struct clk_regmap g12b_sys1_pll_div16_en = {
289 static struct clk_regmap g12a_fclk_div2 = {
326 static struct clk_regmap g12a_fclk_div3 = {
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Dsclk-div.c26 meson_sclk_div_data(struct clk_regmap *clk) in meson_sclk_div_data()
102 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_round_rate()
111 static void sclk_apply_ratio(struct clk_regmap *clk, in sclk_apply_ratio()
127 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_set_duty_cycle()
141 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_get_duty_cycle()
157 static void sclk_apply_divider(struct clk_regmap *clk, in sclk_apply_divider()
169 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_set_rate()
184 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_recalc_rate()
192 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_enable()
202 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_disable()
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Dg12a-aoclk.c44 static struct clk_regmap g12a_aoclk_##_name = { \
76 static struct clk_regmap g12a_aoclk_cts_oscin = {
103 static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
118 static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
157 static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
176 static struct clk_regmap g12a_aoclk_32k_by_oscin = {
194 static struct clk_regmap g12a_aoclk_cec_pre = {
209 static struct clk_regmap g12a_aoclk_cec_div = {
248 static struct clk_regmap g12a_aoclk_cec_sel = {
267 static struct clk_regmap g12a_aoclk_cec = {
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Dclk-regmap.h23 struct clk_regmap { struct
29 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
31 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
51 clk_get_regmap_gate_data(struct clk_regmap *clk) in clk_get_regmap_gate_data()
79 clk_get_regmap_div_data(struct clk_regmap *clk) in clk_get_regmap_div_data()
109 clk_get_regmap_mux_data(struct clk_regmap *clk) in clk_get_regmap_mux_data()
118 struct clk_regmap _name = { \
Daxg.c25 static struct clk_regmap axg_fixed_pll_dco = {
68 static struct clk_regmap axg_fixed_pll = {
89 static struct clk_regmap axg_sys_pll_dco = {
127 static struct clk_regmap axg_sys_pll = {
186 static struct clk_regmap axg_gp0_pll_dco = {
232 static struct clk_regmap axg_gp0_pll = {
258 static struct clk_regmap axg_hifi_pll_dco = {
305 static struct clk_regmap axg_hifi_pll = {
334 static struct clk_regmap axg_fclk_div2 = {
361 static struct clk_regmap axg_fclk_div3 = {
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Daxg-aoclk.c35 static struct clk_regmap axg_aoclk_##_name = { \
59 static struct clk_regmap axg_aoclk_cts_oscin = {
74 static struct clk_regmap axg_aoclk_32k_pre = {
99 static struct clk_regmap axg_aoclk_32k_div = {
138 static struct clk_regmap axg_aoclk_32k_sel = {
157 static struct clk_regmap axg_aoclk_32k = {
173 static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
192 static struct clk_regmap axg_aoclk_clk81 = {
211 static struct clk_regmap axg_aoclk_saradc_mux = {
228 static struct clk_regmap axg_aoclk_saradc_div = {
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Dmeson8b.c64 static struct clk_regmap meson8b_fixed_pll_dco = {
109 static struct clk_regmap meson8b_fixed_pll = {
130 static struct clk_regmap meson8b_hdmi_pll_dco = {
176 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
194 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
212 static struct clk_regmap meson8b_sys_pll_dco = {
253 static struct clk_regmap meson8b_sys_pll = {
284 static struct clk_regmap meson8b_fclk_div2 = {
312 static struct clk_regmap meson8b_fclk_div3 = {
340 static struct clk_regmap meson8b_fclk_div4 = {
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Dgxbb-aoclk.c24 static struct clk_regmap _name##_ao = { \
47 static struct clk_regmap ao_cts_oscin = {
62 static struct clk_regmap ao_32k_pre = {
85 static struct clk_regmap ao_32k_div = {
122 static struct clk_regmap ao_32k_sel = {
141 static struct clk_regmap ao_32k = {
155 static struct clk_regmap ao_cts_rtc_oscin = {
177 static struct clk_regmap ao_clk81 = {
196 static struct clk_regmap ao_cts_cec = {
237 static struct clk_regmap *gxbb_aoclk[] = {
Dclk-regmap.c12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled()
62 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_recalc_rate()
81 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_round_rate()
107 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_set_rate()
139 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_get_parent()
155 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_set_parent()
167 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_determine_rate()
Dclk-cpu-dyndiv.c14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate()
34 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_round_rate()
43 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_set_rate()
Dclk-pll.c41 meson_clk_pll_data(struct clk_regmap *clk) in meson_clk_pll_data()
75 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_recalc_rate()
248 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_round_rate()
274 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_wait_lock()
291 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_init()
306 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_is_enabled()
329 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_enable()
353 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_disable()
366 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_set_rate()
Dclk-mpll.c26 meson_clk_mpll_data(struct clk_regmap *clk) in meson_clk_mpll_data()
78 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_recalc_rate()
94 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_round_rate()
106 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_set_rate()
134 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_init()
Dclk-dualdiv.c31 meson_clk_dualdiv_data(struct clk_regmap *clk) in meson_clk_dualdiv_data()
50 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_dualdiv_recalc_rate()
92 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_dualdiv_round_rate()
106 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_dualdiv_set_rate()
Dmeson8-ddr.c25 static struct clk_regmap meson8_ddr_pll_dco = {
63 static struct clk_regmap meson8_ddr_pll = {
88 static struct clk_regmap *const meson8_ddr_clk_regmaps[] = {
Dvid-pll-div.c14 meson_vid_pll_div_data(struct clk_regmap *clk) in meson_vid_pll_div_data()
78 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vid_pll_div_recalc_rate()
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dclk-regmap.h20 struct clk_regmap { struct
28 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
30 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
Dclk-regmap.c24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap()
50 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_enable_regmap()
74 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_disable_regmap()
96 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) in devm_clk_register_regmap()
Dclk-regmap-divider.c22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
61 struct clk_regmap *clkr = &divider->clkr; in div_recalc_rate()
Dclk-rcg.h85 struct clk_regmap clkr;
123 struct clk_regmap clkr;
150 struct clk_regmap clkr;
Dclk-regmap-mux.c21 struct clk_regmap *clkr = to_clk_regmap(hw); in mux_get_parent()
39 struct clk_regmap *clkr = to_clk_regmap(hw); in mux_set_parent()
Dcommon.h9 struct clk_regmap;
24 struct clk_regmap **clks;
/kernel/linux/linux-5.10/drivers/clk/nxp/
Dclk-lpc32xx.c74 static struct regmap *clk_regmap; variable
393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
398 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable()
406 regmap_update_bits(clk_regmap, clk->reg, in clk_mask_disable()
415 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_is_enabled()
431 regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable); in clk_pll_enable()
434 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_enable()
449 regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0); in clk_pll_disable()
457 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_is_enabled()
480 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_recalc_rate()
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