Searched refs:clock_limits (Results 1 – 10 of 10) sorted by relevance
230 .clock_limits = {341 .clock_limits = {2991 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;2992 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;3014 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;3015 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;3020 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;3021 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;3034 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;3035 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;[all …]
165 .clock_limits = {1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()1039 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()1407 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in update_bw_bounding_box() local1421 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in update_bw_bounding_box()1427 clock_limits[i].state = i; in update_bw_bounding_box()1428 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in update_bw_bounding_box()1429 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in update_bw_bounding_box()1430 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in update_bw_bounding_box()1431 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in update_bw_bounding_box()[all …]
171 .clock_limits = {1806 dcn3_0_soc.clock_limits[i].state = in init_soc_bounding_box()1807 le32_to_cpu(bb->clock_limits[i].state); in init_soc_bounding_box()1808 dcn3_0_soc.clock_limits[i].dcfclk_mhz = in init_soc_bounding_box()1809 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); in init_soc_bounding_box()1810 dcn3_0_soc.clock_limits[i].fabricclk_mhz = in init_soc_bounding_box()1811 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); in init_soc_bounding_box()1812 dcn3_0_soc.clock_limits[i].dispclk_mhz = in init_soc_bounding_box()1813 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); in init_soc_bounding_box()1814 dcn3_0_soc.clock_limits[i].dppclk_mhz = in init_soc_bounding_box()[all …]
246 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()249 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()250 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()251 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()252 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()264 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()265 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()266 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()267 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()268 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()[all …]
73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1639 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2056 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()