/kernel/linux/linux-5.10/arch/alpha/kernel/ |
D | core_tsunami.c | 181 volatile unsigned long *csr; in tsunami_pci_tbi() local 186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi() 188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi() 194 *csr = value; in tsunami_pci_tbi() 196 *csr; in tsunami_pci_tbi() 227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write() 231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write() 232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write() 233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write() 251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip() [all …]
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D | core_wildfire.c | 121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose() 122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose() 123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose() 125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose() 126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose() 127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose() 129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose() 130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose() 131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose() 133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose() [all …]
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D | core_titan.c | 207 volatile unsigned long *csr; in titan_pci_tbi() local 220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi() 222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi() 229 *csr = value; in titan_pci_tbi() 231 *csr; in titan_pci_tbi() 240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp() 293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port() 294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port() 295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port() 297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port() [all …]
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D | sys_marvel.c | 96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl() 98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl() 174 volatile unsigned long *csr, in io7_redirect_irq() argument 179 val = *csr; in io7_redirect_irq() 183 *csr = val; in io7_redirect_irq() 185 *csr; in io7_redirect_irq() 196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi() 200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi() 202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi() 213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi() [all …]
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D | err_marvel.c | 818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error() 822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error() 843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error() 844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error() 845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error() 846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error() 847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error() 848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error() 849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error() 850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error() [all …]
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D | core_marvel.c | 61 q = ev7csr->csr; in read_ev7_csr() 73 ev7csr->csr = q; in write_ev7_csr() 184 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors() 185 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors() 186 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors() 187 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors() 195 p7csrs->PO7_ERROR_SUM.csr = -1UL; in io7_clear_errors() 196 p7csrs->PO7_UNCRR_SYM.csr = -1UL; in io7_clear_errors() 197 p7csrs->PO7_CRRCT_SYM.csr = -1UL; in io7_clear_errors() 268 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose() [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
D | intel_csr.c | 302 u32 *payload = dev_priv->csr.dmc_payload; in intel_csr_load_program() 311 if (!dev_priv->csr.dmc_payload) { in intel_csr_load_program() 317 fw_size = dev_priv->csr.dmc_fw_size; in intel_csr_load_program() 328 for (i = 0; i < dev_priv->csr.mmio_count; i++) { in intel_csr_load_program() 329 intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i], in intel_csr_load_program() 330 dev_priv->csr.mmiodata[i]); in intel_csr_load_program() 333 dev_priv->csr.dc_state = 0; in intel_csr_load_program() 382 static u32 parse_csr_fw_dmc(struct intel_csr *csr, in parse_csr_fw_dmc() argument 391 BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || in parse_csr_fw_dmc() 392 ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); in parse_csr_fw_dmc() [all …]
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/kernel/linux/linux-5.10/arch/sparc/kernel/ |
D | ebus.c | 74 u32 csr = 0; in ebus_dma_irq() local 77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq() 78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq() 81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq() 85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq() 87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq() 99 u32 csr; in ebus_dma_register() local 113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register() 116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register() 118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register() [all …]
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/kernel/linux/linux-5.10/drivers/usb/musb/ |
D | musb_gadget.c | 229 u16 fifo_count = 0, csr; in txstate() local 248 csr = musb_readw(epio, MUSB_TXCSR); in txstate() 254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate() 256 musb_ep->end_point.name, csr); in txstate() 260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate() 262 musb_ep->end_point.name, csr); in txstate() 268 csr); in txstate() 301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate() 303 musb_writew(epio, MUSB_TXCSR, csr in txstate() 305 csr &= ~MUSB_TXCSR_DMAMODE; in txstate() [all …]
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D | musb_gadget_ep0.c | 243 u16 csr; in service_zero_data_request() local 266 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request() 267 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request() 269 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request() 272 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request() 274 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request() 275 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request() 277 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request() 279 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request() 403 u16 csr; in service_zero_data_request() local [all …]
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D | musb_host.c | 90 u16 csr; in musb_h_tx_flush_fifo() local 93 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo() 94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo() 95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; in musb_h_tx_flush_fifo() 96 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo() 97 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo() 115 ep->epnum, csr)) in musb_h_tx_flush_fifo() 124 u16 csr; in musb_h_ep0_flush_fifo() local 129 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo() 130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo() [all …]
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D | musb_cppi41.c | 56 u16 csr; in save_rx_toggle() local 64 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle() 65 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in save_rx_toggle() 74 u16 csr; in update_rx_toggle() local 83 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in update_rx_toggle() 84 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in update_rx_toggle() 92 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; in update_rx_toggle() 93 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); in update_rx_toggle() 105 u16 csr; in musb_is_tx_fifo_empty() local 108 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty() [all …]
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D | musbhsdma.c | 152 u16 csr = 0; in configure_channel() local 158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel() 161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel() 164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel() 178 csr); in configure_channel() 228 u16 csr; in dma_channel_abort() local 239 csr = musb_readw(mbase, offset); in dma_channel_abort() 240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in dma_channel_abort() 241 musb_writew(mbase, offset, csr); in dma_channel_abort() 242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort() [all …]
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/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/ |
D | icp_qat_hal.h | 90 #define SET_CAP_CSR(handle, csr, val) \ argument 91 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val) 92 #define GET_CAP_CSR(handle, csr) \ argument 93 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr) 94 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val) argument 95 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr) argument 99 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr)) argument 100 #define SET_AE_CSR(handle, ae, csr, val) \ argument 101 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val) 102 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
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D | adf_hw_arbiter.c | 38 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local 46 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg); in adf_init_arb() 50 WRITE_CSR_ARB_WQCFG(csr, i, i); in adf_init_arb() 59 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i)); in adf_init_arb() 75 void __iomem *csr; in adf_exit_arb() local 81 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb() 85 WRITE_CSR_ARB_SARCONFIG(csr, i, 0); in adf_exit_arb() 89 WRITE_CSR_ARB_WQCFG(csr, i, 0); in adf_exit_arb() 93 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0); in adf_exit_arb() 97 WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0); in adf_exit_arb()
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/kernel/linux/linux-5.10/drivers/watchdog/ |
D | shwdt.c | 85 u8 csr; in sh_wdt_start() local 95 csr = sh_wdt_read_csr(); in sh_wdt_start() 96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start() 97 sh_wdt_write_csr(csr); in sh_wdt_start() 109 csr = sh_wdt_read_csr(); in sh_wdt_start() 110 csr |= WTCSR_TME; in sh_wdt_start() 111 csr &= ~WTCSR_RSTS; in sh_wdt_start() 112 sh_wdt_write_csr(csr); in sh_wdt_start() 115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start() 116 csr &= ~RSTCSR_RSTS; in sh_wdt_start() [all …]
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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/ |
D | adc.c | 16 unsigned char csr; in adc_single() local 22 csr = __raw_readb(ADCSR); in adc_single() 23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single() 24 __raw_writeb(csr, ADCSR); in adc_single() 27 csr = __raw_readb(ADCSR); in adc_single() 28 } while ((csr & ADCSR_ADF) == 0); in adc_single() 30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single() 31 __raw_writeb(csr, ADCSR); in adc_single()
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/kernel/linux/linux-5.10/drivers/scsi/ |
D | sun3_scsi.c | 73 unsigned short csr; /* control/status reg */ member 196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local 200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr() 203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr() 204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr() 206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr() 211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr() 242 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup() 243 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup() 248 dregs->csr |= CSR_SEND; in sun3scsi_dma_setup() [all …]
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D | sun3x_esp.c | 86 u32 csr; in sun3x_esp_dma_drain() local 89 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain() 90 if (!(csr & DMA_FIFO_ISDRAIN)) in sun3x_esp_dma_drain() 93 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sun3x_esp_dma_drain() 131 u32 csr; in sun3x_esp_send_dma_cmd() local 137 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd() 138 csr |= DMA_ENABLE; in sun3x_esp_send_dma_cmd() 140 csr |= DMA_ST_WRITE; in sun3x_esp_send_dma_cmd() 142 csr &= ~DMA_ST_WRITE; in sun3x_esp_send_dma_cmd() 143 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd() [all …]
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/kernel/linux/linux-5.10/arch/riscv/include/asm/ |
D | csr.h | 157 #define csr_swap(csr, val) \ argument 160 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 166 #define csr_read(csr) \ argument 169 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 175 #define csr_write(csr, val) \ argument 178 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 183 #define csr_read_set(csr, val) \ argument 186 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 192 #define csr_set(csr, val) \ argument 195 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ [all …]
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/kernel/linux/linux-5.10/sound/soc/intel/atom/sst/ |
D | sst_loader.c | 57 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local 60 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld() 62 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld() 64 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld() 65 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld() 66 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld() 68 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld() 70 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld() 71 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld() 73 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld() [all …]
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/kernel/linux/linux-5.10/drivers/usb/gadget/udc/ |
D | at91_udc.c | 111 u32 csr; in proc_ep_show() local 118 csr = __raw_readl(ep->creg); in proc_ep_show() 132 csr, in proc_ep_show() 133 (csr & 0x07ff0000) >> 16, in proc_ep_show() 134 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show() 135 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show() 136 types[(csr & 0x700) >> 8], in proc_ep_show() 139 (!(csr & 0x700)) in proc_ep_show() 140 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show() 142 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show() [all …]
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/kernel/linux/linux-5.10/arch/mips/dec/ |
D | kn02-irq.c | 30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local 34 *csr = cached_kn02_csr; in unmask_kn02_irq() 39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local 43 *csr = cached_kn02_csr; in mask_kn02_irq() 62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local 68 *csr = cached_kn02_csr; in init_kn02_irqs()
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/kernel/linux/linux-5.10/drivers/pcmcia/ |
D | pxa2xx_sharpsl.c | 58 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local 66 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state() 67 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state() 75 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state() 80 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); in sharpsl_pcmcia_socket_state() 91 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state() 92 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state() 93 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state() 94 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state() 95 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state() [all …]
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/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/ |
D | cvmx-interrupt-rsl.c | 53 union cvmx_asxx_int_en csr; in __cvmx_interrupt_asxx_enable() local 65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); in __cvmx_interrupt_asxx_enable() 66 csr.s.txpsh = mask; in __cvmx_interrupt_asxx_enable() 67 csr.s.txpop = mask; in __cvmx_interrupt_asxx_enable() 68 csr.s.ovrflw = mask; in __cvmx_interrupt_asxx_enable() 69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); in __cvmx_interrupt_asxx_enable()
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