Searched refs:cw4 (Results 1 – 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_dcn30.c | 121 const struct dmub_window *cw4, in dmub_dcn30_setup_windows() argument
154 offset = cw4->offset; in dmub_dcn30_setup_windows()
160 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn30_setup_windows()
162 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn30_setup_windows()
169 cw4->region.top - cw4->region.base - 1, in dmub_dcn30_setup_windows()
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| D | dmub_dcn20.c | 180 const struct dmub_window *cw4, in dmub_dcn20_setup_windows() argument
216 dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
222 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn20_setup_windows()
224 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn20_setup_windows()
231 cw4->region.top - cw4->region.base - 1, in dmub_dcn20_setup_windows()
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| D | dmub_srv.c | 388 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
431 cw4.offset.quad_part = mail_fb->gpu_addr; in dmub_srv_hw_init()
432 cw4.region.base = DMUB_CW4_BASE; in dmub_srv_hw_init()
433 cw4.region.top = cw4.region.base + mail_fb->size; in dmub_srv_hw_init()
435 inbox1.base = cw4.region.base; in dmub_srv_hw_init()
436 inbox1.top = cw4.region.top; in dmub_srv_hw_init()
451 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, in dmub_srv_hw_init()
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| D | dmub_dcn30.h | 44 const struct dmub_window *cw4,
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| D | dmub_dcn20.h | 172 const struct dmub_window *cw4,
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/ |
| D | dmub_srv.h | 248 const struct dmub_window *cw4,
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