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Searched refs:dml_input (Results 1 – 3 of 3) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()
119 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()
139 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx… in dcn3_build_wm_range_table()
140 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()
141 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h117 } dml_input; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c2232 …k_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_u… in dcn30_calculate_wm_and_dlg()
2233 …r_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_ex… in dcn30_calculate_wm_and_dlg()
2234 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; in dcn30_calculate_wm_and_dlg()
2289 …r_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_ex… in dcn30_calculate_wm_and_dlg()
2290 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; in dcn30_calculate_wm_and_dlg()
2315 …k_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_u… in dcn30_calculate_wm_and_dlg()
2316 …r_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_ex… in dcn30_calculate_wm_and_dlg()
2317 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; in dcn30_calculate_wm_and_dlg()
2358 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg()