Searched refs:dpm_level_enable_mask (Results 1 – 13 of 13) sorted by relevance
2629 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3290 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3344 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()3808 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3811 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3818 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3821 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3828 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3831 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3928 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()[all …]
238 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member
2694 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_highest()2696 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_dpm_highest()2708 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()2710 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()2723 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { in smu7_force_dpm_highest()2725 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; in smu7_force_dpm_highest()2749 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2752 data->dpm_level_enable_mask.sclk_dpm_enable_mask, in smu7_upload_dpm_level_enable_mask()2757 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2760 data->dpm_level_enable_mask.mclk_dpm_enable_mask, in smu7_upload_dpm_level_enable_mask()[all …]
294 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; member
369 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; member
372 struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; member
496 struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; member
595 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in vegam_populate_smc_link_level()911 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in vegam_populate_all_graphic_levels()916 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()927 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()928 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()932 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()933 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()938 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()1069 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in vegam_populate_all_memory_levels()1074 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_memory_levels()
850 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in fiji_populate_smc_link_level()1044 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()1056 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1057 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1061 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1062 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1067 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1259 data->dpm_level_enable_mask.mclk_dpm_enable_mask = in fiji_populate_all_memory_levels()
532 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in tonga_populate_smc_link_level()732 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()745 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()748 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()749 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()754 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()755 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()761 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()1131 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in tonga_populate_all_memory_levels()
501 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()1016 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()1339 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in ci_populate_all_memory_levels()2877 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_update_uvd_smc_table()2881 data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_update_uvd_smc_table()2886 data->dpm_level_enable_mask.uvd_dpm_enable_mask, in ci_update_uvd_smc_table()2909 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_update_vce_smc_table()2913 data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_update_vce_smc_table()2918 data->dpm_level_enable_mask.vce_dpm_enable_mask, in ci_update_vce_smc_table()
792 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in polaris10_populate_smc_link_level()1021 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()1034 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1035 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1039 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1040 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1045 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1165 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in polaris10_populate_all_memory_levels()
789 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in iceland_populate_smc_link_level()1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()1005 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1016 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1383 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in iceland_populate_all_memory_levels()