Searched refs:flush_mask (Results 1 – 12 of 12) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
D | mdp5_ctl.c | 38 u32 flush_mask; member 471 u32 flush_mask) in fix_sw_flush() argument 476 (!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit)) in fix_sw_flush() 485 static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, in fix_for_single_flush() argument 491 DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask); in fix_for_single_flush() 493 ctl_mgr->single_flush_pending_mask |= (*flush_mask); in fix_for_single_flush() 494 *flush_mask = 0; in fix_for_single_flush() 498 *flush_mask = ctl_mgr->single_flush_pending_mask; in fix_for_single_flush() 504 DBG("Single FLUSH mask %x,ID %d", *flush_mask, in fix_for_single_flush() 528 u32 flush_mask, bool start) in mdp5_ctl_commit() argument [all …]
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D | mdp5_crtc.c | 87 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) in crtc_flush() argument 96 DBG("%s: flush=%08x", crtc->name, flush_mask); in crtc_flush() 98 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush() 111 uint32_t flush_mask = 0; in crtc_flush_all() local 120 flush_mask |= mdp5_plane_get_flush(plane); in crtc_flush_all() 124 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); in crtc_flush_all() 128 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); in crtc_flush_all() 130 return crtc_flush(crtc, flush_mask); in crtc_flush_all() 949 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); in mdp5_crtc_cursor_set() local 1012 crtc_flush(crtc, flush_mask); in mdp5_crtc_cursor_set() [all …]
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D | mdp5_mixer.h | 20 uint32_t flush_mask; /* used to commit LM registers */ member
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D | mdp5_pipe.h | 23 uint32_t flush_mask; /* used to commit pipe registers */ member
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D | mdp5_ctl.h | 73 u32 flush_mask, bool start);
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D | mdp5_mixer.c | 165 mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id); in mdp5_mixer_init()
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D | mdp5_pipe.c | 172 hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); in mdp5_pipe_init()
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D | mdp5_plane.c | 1072 mask = pstate->hwpipe->flush_mask; in mdp5_plane_get_flush() 1075 mask |= pstate->r_hwpipe->flush_mask; in mdp5_plane_get_flush()
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
D | dpu_crtc.c | 130 u32 flush_mask; in _dpu_crtc_blend_setup_mixer() local 143 dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); in _dpu_crtc_blend_setup_mixer() 174 mixer[lm_idx].flush_mask |= flush_mask; in _dpu_crtc_blend_setup_mixer() 204 mixer[i].flush_mask = 0; in _dpu_crtc_blend_setup() 221 mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, in _dpu_crtc_blend_setup() 225 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_blend_setup() 231 mixer[i].flush_mask); in _dpu_crtc_blend_setup() 474 mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl, in _dpu_crtc_setup_cp_blocks() 478 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_setup_cp_blocks() 483 mixer[i].flush_mask); in _dpu_crtc_setup_cp_blocks()
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D | dpu_encoder_phys_vid.c | 432 u32 flush_mask = 0; in dpu_encoder_phys_vid_enable() local 455 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx); in dpu_encoder_phys_vid_enable() 456 ctl->ops.update_pending_flush(ctl, flush_mask); in dpu_encoder_phys_vid_enable() 468 ctl->idx - CTL_0, flush_mask, intf_flush_mask); in dpu_encoder_phys_vid_enable()
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D | dpu_crtc.h | 85 u32 flush_mask; member
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D | dpu_encoder_phys_cmd.c | 440 u32 flush_mask = 0; in dpu_encoder_phys_cmd_enable_helper() local 455 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx); in dpu_encoder_phys_cmd_enable_helper() 456 ctl->ops.update_pending_flush(ctl, flush_mask); in dpu_encoder_phys_cmd_enable_helper()
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