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Searched refs:hwmgr (Results 1 – 25 of 91) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dhwmgr.c49 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
50 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
51 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
52 extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
53 extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
54 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
56 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
57 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
58 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
59 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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Dhardwaremanager.c39 int phm_setup_asic(struct pp_hwmgr *hwmgr) in phm_setup_asic() argument
41 PHM_FUNC_CHECK(hwmgr); in phm_setup_asic()
43 if (NULL != hwmgr->hwmgr_func->asic_setup) in phm_setup_asic()
44 return hwmgr->hwmgr_func->asic_setup(hwmgr); in phm_setup_asic()
49 int phm_power_down_asic(struct pp_hwmgr *hwmgr) in phm_power_down_asic() argument
51 PHM_FUNC_CHECK(hwmgr); in phm_power_down_asic()
53 if (NULL != hwmgr->hwmgr_func->power_off_asic) in phm_power_down_asic()
54 return hwmgr->hwmgr_func->power_off_asic(hwmgr); in phm_power_down_asic()
59 int phm_set_power_state(struct pp_hwmgr *hwmgr, in phm_set_power_state() argument
65 PHM_FUNC_CHECK(hwmgr); in phm_set_power_state()
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Dpp_psm.c29 int psm_init_power_state_table(struct pp_hwmgr *hwmgr) in psm_init_power_state_table() argument
37 if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL) in psm_init_power_state_table()
40 if (hwmgr->hwmgr_func->get_power_state_size == NULL) in psm_init_power_state_table()
43 hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr); in psm_init_power_state_table()
45 hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) + in psm_init_power_state_table()
53 hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL); in psm_init_power_state_table()
54 if (hwmgr->ps == NULL) in psm_init_power_state_table()
57 hwmgr->request_ps = kzalloc(size, GFP_KERNEL); in psm_init_power_state_table()
58 if (hwmgr->request_ps == NULL) { in psm_init_power_state_table()
59 kfree(hwmgr->ps); in psm_init_power_state_table()
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Dsmu7_thermal.c29 int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, in smu7_fan_ctrl_get_fan_speed_info() argument
32 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_info()
41 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { in smu7_fan_ctrl_get_fan_speed_info()
44 fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; in smu7_fan_ctrl_get_fan_speed_info()
45 fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; in smu7_fan_ctrl_get_fan_speed_info()
54 int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, in smu7_fan_ctrl_get_fan_speed_percent() argument
61 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_percent()
64 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_fan_ctrl_get_fan_speed_percent()
66 duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_fan_ctrl_get_fan_speed_percent()
83 int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) in smu7_fan_ctrl_get_fan_speed_rpm() argument
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Dvega10_thermal.c32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) in vega10_get_current_rpm() argument
34 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm); in vega10_get_current_rpm()
38 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, in vega10_fan_ctrl_get_fan_speed_info() argument
42 if (hwmgr->thermal_controller.fanInfo.bNoFan) in vega10_fan_ctrl_get_fan_speed_info()
51 hwmgr->thermal_controller.fanInfo. in vega10_fan_ctrl_get_fan_speed_info()
56 hwmgr->thermal_controller.fanInfo.ulMinRPM; in vega10_fan_ctrl_get_fan_speed_info()
58 hwmgr->thermal_controller.fanInfo.ulMaxRPM; in vega10_fan_ctrl_get_fan_speed_info()
67 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, in vega10_fan_ctrl_get_fan_speed_percent() argument
73 if (hwmgr->thermal_controller.fanInfo.bNoFan) in vega10_fan_ctrl_get_fan_speed_percent()
76 if (vega10_get_current_rpm(hwmgr, &current_rpm)) in vega10_fan_ctrl_get_fan_speed_percent()
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Dsmu8_hwmgr.c68 static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, in smu8_get_eclk_level() argument
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
99 static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, in smu8_get_sclk_level() argument
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
129 static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, in smu8_get_uvd_level() argument
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_get_uvd_level()
160 static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) in smu8_get_max_sclk_level() argument
162 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_max_sclk_level()
165 smum_send_msg_to_smc(hwmgr, in smu8_get_max_sclk_level()
174 static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) in smu8_initialize_dpm_defaults() argument
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Dsmu10_hwmgr.c51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, in smu10_display_clock_voltage_request() argument
54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_display_clock_voltage_request()
79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL); in smu10_display_clock_voltage_request()
101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) in smu10_initialize_dpm_defaults() argument
103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); in smu10_initialize_dpm_defaults()
113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu10_initialize_dpm_defaults()
116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu10_initialize_dpm_defaults()
119 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu10_initialize_dpm_defaults()
124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, in smu10_construct_max_power_limits_table() argument
131 struct pp_hwmgr *hwmgr) in smu10_init_dynamic_state_adjustment_rule_settings() argument
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Dsmu7_clockpowergating.c28 static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu7_enable_disable_uvd_dpm() argument
30 return smum_send_msg_to_smc(hwmgr, enable ? in smu7_enable_disable_uvd_dpm()
36 static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu7_enable_disable_vce_dpm() argument
38 return smum_send_msg_to_smc(hwmgr, enable ? in smu7_enable_disable_vce_dpm()
44 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) in smu7_update_uvd_dpm() argument
47 smum_update_smc_table(hwmgr, SMU_UVD_TABLE); in smu7_update_uvd_dpm()
48 return smu7_enable_disable_uvd_dpm(hwmgr, !bgate); in smu7_update_uvd_dpm()
51 static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate) in smu7_update_vce_dpm() argument
54 smum_update_smc_table(hwmgr, SMU_VCE_TABLE); in smu7_update_vce_dpm()
55 return smu7_enable_disable_vce_dpm(hwmgr, !bgate); in smu7_update_vce_dpm()
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Dsmu7_hwmgr.c113 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
142 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) in smu7_get_mc_microcode_version() argument
144 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); in smu7_get_mc_microcode_version()
146 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); in smu7_get_mc_microcode_version()
151 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) in smu7_get_current_pcie_speed() argument
156 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_speed()
162 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) in smu7_get_current_pcie_lane_number() argument
167 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()
182 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) in smu7_enable_smc_voltage_controller() argument
184 if (hwmgr->chip_id == CHIP_VEGAM) { in smu7_enable_smc_voltage_controller()
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Dprocesspptables.c50 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr, in get_vce_table_offset() argument
74 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_offset() argument
77 uint16_t table_offset = get_vce_table_offset(hwmgr, in get_vce_clock_info_array_offset()
86 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_size() argument
89 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_info_array_size()
102 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_offset() argument
105 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_voltage_limit_table_offset()
109 return table_offset + get_vce_clock_info_array_size(hwmgr, in get_vce_clock_voltage_limit_table_offset()
115 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_size() argument
118 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in get_vce_clock_voltage_limit_table_size()
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Dvega12_hwmgr.c58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) in vega12_set_default_registry_data() argument
68 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_default_registry_data()
136 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); in vega12_set_default_registry_data()
139 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) in vega12_set_features_platform_caps() argument
142 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_features_platform_caps()
143 struct amdgpu_device *adev = hwmgr->adev; in vega12_set_features_platform_caps()
146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
149 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
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Dvega12_thermal.c32 static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) in vega12_get_current_rpm() argument
34 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, in vega12_get_current_rpm()
43 int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, in vega12_fan_ctrl_get_fan_speed_info() argument
55 int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) in vega12_fan_ctrl_get_fan_speed_rpm() argument
59 return vega12_get_current_rpm(hwmgr, speed); in vega12_fan_ctrl_get_fan_speed_rpm()
69 static int vega12_enable_fan_control_feature(struct pp_hwmgr *hwmgr) in vega12_enable_fan_control_feature() argument
72 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_enable_fan_control_feature()
76 hwmgr, true, in vega12_enable_fan_control_feature()
87 static int vega12_disable_fan_control_feature(struct pp_hwmgr *hwmgr) in vega12_disable_fan_control_feature() argument
90 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_disable_fan_control_feature()
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Dvega20_thermal.c32 static int vega20_disable_fan_control_feature(struct pp_hwmgr *hwmgr) in vega20_disable_fan_control_feature() argument
34 struct vega20_hwmgr *data = hwmgr->backend; in vega20_disable_fan_control_feature()
39 hwmgr, false, in vega20_disable_fan_control_feature()
51 int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) in vega20_fan_ctrl_stop_smc_fan_control() argument
53 struct vega20_hwmgr *data = hwmgr->backend; in vega20_fan_ctrl_stop_smc_fan_control()
56 return vega20_disable_fan_control_feature(hwmgr); in vega20_fan_ctrl_stop_smc_fan_control()
61 static int vega20_enable_fan_control_feature(struct pp_hwmgr *hwmgr) in vega20_enable_fan_control_feature() argument
63 struct vega20_hwmgr *data = hwmgr->backend; in vega20_enable_fan_control_feature()
68 hwmgr, true, in vega20_enable_fan_control_feature()
80 int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) in vega20_fan_ctrl_start_smc_fan_control() argument
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Dvega10_hwmgr.c116 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) in vega10_set_default_registry_data() argument
118 struct vega10_hwmgr *data = hwmgr->backend; in vega10_set_default_registry_data()
121 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
123 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
125 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
127 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
130 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
132 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
139 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
142 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
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Dprocess_pptables_v1_0.c40 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap) in set_hw_cap() argument
43 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
45 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
55 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) in set_platform_caps() argument
69 hwmgr, in set_platform_caps()
75 hwmgr, in set_platform_caps()
81 hwmgr, in set_platform_caps()
87 hwmgr, in set_platform_caps()
93 hwmgr, in set_platform_caps()
99 hwmgr, in set_platform_caps()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/
Damd_powerplay.c40 struct pp_hwmgr *hwmgr; in amd_powerplay_create() local
45 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); in amd_powerplay_create()
46 if (hwmgr == NULL) in amd_powerplay_create()
49 hwmgr->adev = adev; in amd_powerplay_create()
50 hwmgr->not_vf = !amdgpu_sriov_vf(adev); in amd_powerplay_create()
51 hwmgr->device = amdgpu_cgs_create_device(adev); in amd_powerplay_create()
52 mutex_init(&hwmgr->smu_lock); in amd_powerplay_create()
53 mutex_init(&hwmgr->msg_lock); in amd_powerplay_create()
54 hwmgr->chip_family = adev->family; in amd_powerplay_create()
55 hwmgr->chip_id = adev->asic_type; in amd_powerplay_create()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmumgr.c57 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr) in smum_thermal_avfs_enable() argument
59 if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable) in smum_thermal_avfs_enable()
60 return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr); in smum_thermal_avfs_enable()
65 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) in smum_thermal_setup_fan_table() argument
67 if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table) in smum_thermal_setup_fan_table()
68 return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); in smum_thermal_setup_fan_table()
73 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) in smum_update_sclk_threshold() argument
76 if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold) in smum_update_sclk_threshold()
77 return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr); in smum_update_sclk_threshold()
82 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) in smum_update_smc_table() argument
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Dsmu8_smumgr.c56 static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr) in smu8_get_argument() argument
58 if (hwmgr == NULL || hwmgr->device == NULL) in smu8_get_argument()
61 return cgs_read_register(hwmgr->device, in smu8_get_argument()
66 static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, in smu8_send_msg_to_smc_with_parameter() argument
73 if (hwmgr == NULL || hwmgr->device == NULL) in smu8_send_msg_to_smc_with_parameter()
76 result = PHM_WAIT_FIELD_UNEQUAL(hwmgr, in smu8_send_msg_to_smc_with_parameter()
80 uint32_t val = cgs_read_register(hwmgr->device, in smu8_send_msg_to_smc_with_parameter()
88 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter); in smu8_send_msg_to_smc_with_parameter()
90 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); in smu8_send_msg_to_smc_with_parameter()
91 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); in smu8_send_msg_to_smc_with_parameter()
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Dsmu7_smumgr.c38 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit) in smu7_set_smc_sram_address() argument
43 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr); in smu7_set_smc_sram_address()
44 …PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_A… in smu7_set_smc_sram_address()
49 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, ui… in smu7_copy_bytes_from_smc() argument
63 smu7_read_smc_sram_dword(hwmgr, addr, &data, limit); in smu7_copy_bytes_from_smc()
73 smu7_read_smc_sram_dword(hwmgr, addr, &data, limit); in smu7_copy_bytes_from_smc()
85 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, in smu7_copy_bytes_to_smc() argument
103 result = smu7_set_smc_sram_address(hwmgr, addr, limit); in smu7_copy_bytes_to_smc()
108 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data); in smu7_copy_bytes_to_smc()
119 result = smu7_set_smc_sram_address(hwmgr, addr, limit); in smu7_copy_bytes_to_smc()
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Dci_smumgr.c95 static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr, in ci_set_smc_sram_address() argument
104 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
105 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
109 static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, in ci_copy_bytes_to_smc() argument
130 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
135 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
146 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
152 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
166 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
171 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
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Diceland_smumgr.c109 static int iceland_start_smc(struct pp_hwmgr *hwmgr) in iceland_start_smc() argument
111 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_start_smc()
117 static void iceland_reset_smc(struct pp_hwmgr *hwmgr) in iceland_reset_smc() argument
119 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_reset_smc()
125 static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr) in iceland_stop_smc_clock() argument
127 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_stop_smc_clock()
132 static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr) in iceland_start_smc_clock() argument
134 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_start_smc_clock()
139 static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr) in iceland_smu_start_smc() argument
142 smu7_program_jump_on_start(hwmgr); in iceland_smu_start_smc()
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Dfiji_smumgr.c99 static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) in fiji_start_smu_in_protection_mode() argument
107 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
110 result = smu7_upload_smu_firmware_image(hwmgr); in fiji_start_smu_in_protection_mode()
115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
130 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
137 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, in fiji_start_smu_in_protection_mode()
140 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000, NULL); in fiji_start_smu_in_protection_mode()
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Dpolaris10_smumgr.c96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr) in polaris10_perform_btc() argument
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); in polaris10_perform_btc()
102 …if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param, in polaris10_perform_btc()
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc()
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()
120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) in polaris10_setup_graphics_level_structure() argument
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in polaris10_setup_graphics_level_structure()
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, in polaris10_setup_graphics_level_structure()
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
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Dvegam_smumgr.c82 static int vegam_smu_init(struct pp_hwmgr *hwmgr) in vegam_smu_init() argument
90 hwmgr->smu_backend = smu_data; in vegam_smu_init()
92 if (smu7_init(hwmgr)) { in vegam_smu_init()
100 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) in vegam_start_smu_in_protection_mode() argument
108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
111 result = smu7_upload_smu_firmware_image(hwmgr); in vegam_start_smu_in_protection_mode()
116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in vegam_start_smu_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
126 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); in vegam_start_smu_in_protection_mode()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dhwmgr.h202 int (*smu_init)(struct pp_hwmgr *hwmgr);
203 int (*smu_fini)(struct pp_hwmgr *hwmgr);
204 int (*start_smu)(struct pp_hwmgr *hwmgr);
205 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
207 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
208 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
210 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
211 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
212 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
214 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
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