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Searched refs:hws (Results 1 – 25 of 176) sorted by relevance

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/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx8mq.c274 static struct clk_hw **hws; variable
283 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx8mq_clocks_probe()
289 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
291 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
292 hws[IMX8MQ_CLK_32K] = imx_obtain_fixed_clk_hw(np, "ckil"); in imx8mq_clocks_probe()
293 hws[IMX8MQ_CLK_25M] = imx_obtain_fixed_clk_hw(np, "osc_25m"); in imx8mq_clocks_probe()
294 hws[IMX8MQ_CLK_27M] = imx_obtain_fixed_clk_hw(np, "osc_27m"); in imx8mq_clocks_probe()
295 hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mq_clocks_probe()
296 hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mq_clocks_probe()
297 hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mq_clocks_probe()
[all …]
Dclk-imx7d.c377 static struct clk_hw **hws; variable
385 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx7d_clocks_init()
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
394 hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx7d_clocks_init()
395 hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx7d_clocks_init()
402hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
[all …]
Dclk-imx8mn.c285 static struct clk_hw **hws; variable
294 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx8mn_clocks_probe()
300 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
302 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
303 hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); in imx8mn_clocks_probe()
304 hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); in imx8mn_clocks_probe()
305 hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mn_clocks_probe()
306 hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mn_clocks_probe()
307 hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mn_clocks_probe()
308 hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); in imx8mn_clocks_probe()
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Dclk-imx8mm.c292 static struct clk_hw **hws; variable
301 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx8mm_clocks_probe()
307 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
309 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
310 hws[IMX8MM_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); in imx8mm_clocks_probe()
311 hws[IMX8MM_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); in imx8mm_clocks_probe()
312 hws[IMX8MM_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mm_clocks_probe()
313 hws[IMX8MM_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mm_clocks_probe()
314 hws[IMX8MM_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mm_clocks_probe()
315 hws[IMX8MM_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); in imx8mm_clocks_probe()
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Dclk-imx6ul.c71 static struct clk_hw **hws; variable
119 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6ul_clocks_init()
125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
127 hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6ul_clocks_init()
129 hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx6ul_clocks_init()
130 hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx6ul_clocks_init()
133 hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); in imx6ul_clocks_init()
134 hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); in imx6ul_clocks_init()
141hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
142hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
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Dclk-imx6sx.c85 static struct clk_hw **hws; variable
125 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sx_clocks_init()
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
133 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sx_clocks_init()
135 hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx6sx_clocks_init()
136 hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx6sx_clocks_init()
139 hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
140 hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
143 hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1"); in imx6sx_clocks_init()
144 hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2"); in imx6sx_clocks_init()
[all …]
Dclk-imx8mp.c420 static struct clk_hw **hws; variable
442 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL); in imx8mp_clocks_probe()
449 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
451 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
452 hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); in imx8mp_clocks_probe()
453 hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); in imx8mp_clocks_probe()
454 hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mp_clocks_probe()
455 hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mp_clocks_probe()
456 hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mp_clocks_probe()
457 hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); in imx8mp_clocks_probe()
[all …]
Dclk-imx6q.c92 static struct clk_hw **hws; variable
270 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
271 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in mmdc_ch1_disable()
345 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in init_ldb_clks()
346 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { in init_ldb_clks()
398 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in disable_anatop_clocks()
399 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) in disable_anatop_clocks()
437 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6q_clocks_init()
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
445 hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6q_clocks_init()
[all …]
Dclk-imx6sl.c99 static struct clk_hw **hws; variable
187 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sl_clocks_init()
193 hws = clk_hw_data->hws; in imx6sl_clocks_init()
195 hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sl_clocks_init()
196 hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0); in imx6sl_clocks_init()
197 hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0); in imx6sl_clocks_init()
199 hws[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock_hw("anaclk1", 0); in imx6sl_clocks_init()
207hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
208hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
209hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
[all …]
Dclk-imx6sll.c56 static struct clk_hw **hws; variable
84 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
92 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sll_clocks_init()
94 hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx6sll_clocks_init()
95 hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx6sll_clocks_init()
98 hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); in imx6sll_clocks_init()
99 hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); in imx6sll_clocks_init()
115hws[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_sr… in imx6sll_clocks_init()
116hws[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_sr… in imx6sll_clocks_init()
[all …]
Dclk-imx7ulp.c49 struct clk_hw **hws; in imx7ulp_clk_scg1_init() local
52 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END), in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7ulp_clk_scg1_init()
62 hws[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc"); in imx7ulp_clk_scg1_init()
63 hws[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); in imx7ulp_clk_scg1_init()
64 hws[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); in imx7ulp_clk_scg1_init()
65 hws[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); in imx7ulp_clk_scg1_init()
66 hws[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); in imx7ulp_clk_scg1_init()
73hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-efm32gg.c23 struct clk_hw **hws; in efm32gg_cmu_init() local
25 clk_data = kzalloc(struct_size(clk_data, hws, CMU_MAX_CLKS), in efm32gg_cmu_init()
31 hws = clk_data->hws; in efm32gg_cmu_init()
34 hws[i] = ERR_PTR(-ENOENT); in efm32gg_cmu_init()
42 hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0, in efm32gg_cmu_init()
45 hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0", in efm32gg_cmu_init()
47 hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1", in efm32gg_cmu_init()
49 hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2", in efm32gg_cmu_init()
51 hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0", in efm32gg_cmu_init()
53 hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1", in efm32gg_cmu_init()
[all …]
Dclk-clps711x.c56 clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws, in clps711x_clk_init_dt()
108 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = in clps711x_clk_init_dt()
110 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = in clps711x_clk_init_dt()
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = in clps711x_clk_init_dt()
114 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = in clps711x_clk_init_dt()
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] = in clps711x_clk_init_dt()
118 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = in clps711x_clk_init_dt()
122 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = in clps711x_clk_init_dt()
126 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = in clps711x_clk_init_dt()
128 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] = in clps711x_clk_init_dt()
[all …]
Dclk-ast2600.c484 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_g6_clk_probe()
495 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; in aspeed_g6_clk_probe()
525 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; in aspeed_g6_clk_probe()
539 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_g6_clk_probe()
553 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; in aspeed_g6_clk_probe()
561 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; in aspeed_g6_clk_probe()
569 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; in aspeed_g6_clk_probe()
583 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; in aspeed_g6_clk_probe()
591 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw; in aspeed_g6_clk_probe()
599 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw; in aspeed_g6_clk_probe()
[all …]
Dclk-aspeed.c431 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_clk_probe()
441 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; in aspeed_clk_probe()
455 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_clk_probe()
464 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; in aspeed_clk_probe()
479 aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; in aspeed_clk_probe()
487 aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; in aspeed_clk_probe()
497 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; in aspeed_clk_probe()
506 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; in aspeed_clk_probe()
513 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; in aspeed_clk_probe()
521 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; in aspeed_clk_probe()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/
Digt_spinner.c21 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in igt_spinner_init()
22 if (IS_ERR(spin->hws)) { in igt_spinner_init()
23 err = PTR_ERR(spin->hws); in igt_spinner_init()
33 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC); in igt_spinner_init()
34 vaddr = i915_gem_object_pin_map(spin->hws, I915_MAP_WB); in igt_spinner_init()
52 i915_gem_object_unpin_map(spin->hws); in igt_spinner_init()
56 i915_gem_object_put(spin->hws); in igt_spinner_init()
66 static u64 hws_address(const struct i915_vma *hws, in hws_address() argument
69 return hws->node.start + seqno_offset(rq->fence.context); in hws_address()
95 struct i915_vma *hws, *vma; in igt_spinner_create_request() local
[all …]
/kernel/linux/linux-5.10/drivers/clk/x86/
Dclk-fch.c34 static struct clk_hw *hws[ST_MAX_CLKS]; variable
45 hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
47 hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", in fch_clk_probe()
50 hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux", in fch_clk_probe()
55 clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); in fch_clk_probe()
57 hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
61 devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], in fch_clk_probe()
64 hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
67 hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
71 devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE], in fch_clk_probe()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.c32 hws->ctx
34 hws->regs->reg
38 hws->shifts->field_name, hws->masks->field_name
40 void dce_enable_fe_clock(struct dce_hwseq *hws, in dce_enable_fe_clock() argument
53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock() local
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
80 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
97 void dce_set_blender_mode(struct dce_hwseq *hws, in dce_set_blender_mode() argument
129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
138 static void dce_disable_sram_shut_down(struct dce_hwseq *hws) in dce_disable_sram_shut_down() argument
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/kernel/linux/linux-5.10/drivers/isdn/hardware/mISDN/
Diohelper.h25 #define IOFUNC_IO(name, hws, ap) \ argument
27 struct hws *hw = p; \
31 struct hws *hw = p; \
35 struct hws *hw = p; \
39 struct hws *hw = p; \
43 #define IOFUNC_IND(name, hws, ap) \ argument
45 struct hws *hw = p; \
50 struct hws *hw = p; \
55 struct hws *hw = p; \
60 struct hws *hw = p; \
[all …]
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-bcm2711-dvp.c39 struct_size(dvp->data, hws, NR_CLOCKS), in clk_dvp_probe()
60 data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev, in clk_dvp_probe()
66 if (IS_ERR(data->hws[0])) in clk_dvp_probe()
67 return PTR_ERR(data->hws[0]); in clk_dvp_probe()
69 data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev, in clk_dvp_probe()
75 if (IS_ERR(data->hws[1])) { in clk_dvp_probe()
76 ret = PTR_ERR(data->hws[1]); in clk_dvp_probe()
89 clk_hw_unregister_gate(data->hws[1]); in clk_dvp_probe()
92 clk_hw_unregister_gate(data->hws[0]); in clk_dvp_probe()
101 clk_hw_unregister_gate(data->hws[1]); in clk_dvp_remove()
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/kernel/linux/linux-5.10/drivers/ide/
Dide-legacy.c6 static void ide_legacy_init_one(struct ide_hw **hws, struct ide_hw *hw, in ide_legacy_init_one() argument
40 hws[port_no] = hw; in ide_legacy_init_one()
45 struct ide_hw hw[2], *hws[] = { NULL, NULL }; in ide_legacy_device_add() local
50 ide_legacy_init_one(hws, &hw[0], 0, d, config); in ide_legacy_device_add()
51 ide_legacy_init_one(hws, &hw[1], 1, d, config); in ide_legacy_device_add()
53 if (hws[0] == NULL && hws[1] == NULL && in ide_legacy_device_add()
57 return ide_host_add(d, hws, 2, NULL); in ide_legacy_device_add()
/kernel/linux/linux-5.10/drivers/clk/imgtec/
Dclk-boston.c61 onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT), in clk_boston_setup()
73 onecell->hws[BOSTON_CLK_INPUT] = hw; in clk_boston_setup()
80 onecell->hws[BOSTON_CLK_SYS] = hw; in clk_boston_setup()
87 onecell->hws[BOSTON_CLK_CPU] = hw; in clk_boston_setup()
98 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]); in clk_boston_setup()
100 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]); in clk_boston_setup()
102 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]); in clk_boston_setup()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.h87 struct dce_hwseq *hws);
90 struct dce_hwseq *hws,
93 struct dce_hwseq *hws,
97 struct dce_hwseq *hws,
116 struct dce_hwseq *hws,
124 struct dce_hwseq *hws,
130 void dcn20_dccg_init(struct dce_hwseq *hws);
131 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
Ddcn20_hwseq.c58 hws->ctx
60 hws->regs->reg
64 hws->shifts->field_name, hws->masks->field_name
185 struct dce_hwseq *hws, in dcn20_enable_power_gating_plane() argument
225 void dcn20_dccg_init(struct dce_hwseq *hws) in dcn20_dccg_init() argument
250 struct dce_hwseq *hws) in dcn20_disable_vga() argument
277 struct dce_hwseq *hws = dc->hwseq; in dcn20_init_blank() local
335 hws->funcs.wait_for_blank_complete(opp); in dcn20_init_blank()
339 struct dce_hwseq *hws, in dcn20_dsc_pg_control() argument
347 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn20_dsc_pg_control()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c59 hws->ctx
61 hws->regs->reg
65 hws->shifts->field_name, hws->masks->field_name
118 struct dce_hwseq *hws = dc->hwseq; in log_mpc_crc() local
483 struct dce_hwseq *hws, in dcn10_enable_power_gating_plane() argument
505 struct dce_hwseq *hws) in dcn10_disable_vga() argument
538 struct dce_hwseq *hws, in dcn10_dpp_pg_control() argument
545 if (hws->ctx->dc->debug.disable_dpp_power_gate) in dcn10_dpp_pg_control()
590 struct dce_hwseq *hws, in dcn10_hubp_pg_control() argument
597 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn10_hubp_pg_control()
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