Searched refs:initial_offset (Results 1 – 10 of 10) sorted by relevance
176 pps_payload->initial_offset = in drm_dsc_pps_payload_pack()177 cpu_to_be16(dsc_cfg->initial_offset); in drm_dsc_pps_payload_pack()342 vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()371 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
53 to->initial_offset = from->initial_offset; in copy_pps_fields()78 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
158 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_push_si() local214 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_push_si()285 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_packetize_access_units() local318 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_packetize_access_units()356 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_pad_with_nulls() local370 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_pad_with_nulls()
172 u16 initial_offset; member444 __be16 initial_offset; member
41 u16 initial_offset; member426 vdsc_cfg->initial_offset = rc_params->initial_offset; in intel_dsc_compute_params()462 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()719 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
276 nd_btt->initial_offset = 0; in nd_btt_version()291 nd_btt->initial_offset = SZ_4K; in nd_btt_version()
190 int initial_offset; member
34 return offset + nd_btt->initial_offset; in adjust_initial_offset()1698 rawsize = size - nd_btt->initial_offset; in nvdimm_namespace_attach_btt()1702 ARENA_MIN_SIZE + nd_btt->initial_offset); in nvdimm_namespace_attach_btt()
306 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); in dsc_log_pps()513 reg_vals->pps.initial_offset = 6144; in dsc_init_reg_values()629 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()
12161 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) argument