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Searched refs:intel_de_read (Results 1 – 25 of 37) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_combo_phy.c51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
97 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
131 return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && in cnl_combo_phy_enabled()
132 (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT); in cnl_combo_phy_enabled()
155 val = intel_de_read(dev_priv, CHICKEN_MISC_2); in cnl_combo_phys_init()
162 val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0); in cnl_combo_phys_init()
166 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); in cnl_combo_phys_init()
179 val = intel_de_read(dev_priv, CHICKEN_MISC_2); in cnl_combo_phys_uninit()
203 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
[all …]
Dicl_dsi.c42 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
49 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
113 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & in wait_for_cmds_dispatched_to_panel()
164 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
221 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); in dsi_program_swing_and_deemphasis()
228 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); in dsi_program_swing_and_deemphasis()
235 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); in dsi_program_swing_and_deemphasis()
243 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); in dsi_program_swing_and_deemphasis()
251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); in dsi_program_swing_and_deemphasis()
261 tmp = intel_de_read(dev_priv, in dsi_program_swing_and_deemphasis()
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Dintel_dpll_mgr.c417 val = intel_de_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
419 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
420 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
443 val = intel_de_read(dev_priv, PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
577 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
595 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
620 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
640 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1062 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1168 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
[all …]
Dvlv_dsi.c114 u32 val = intel_de_read(dev_priv, reg); in read_data()
234 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
337 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
343 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
349 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
350 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
367 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
388 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
394 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
395 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
Dintel_audio.c305 tmp = intel_de_read(dev_priv, reg_eldv); in intel_eld_uptodate()
311 tmp = intel_de_read(dev_priv, reg_elda); in intel_eld_uptodate()
316 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) in intel_eld_uptodate()
331 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_disable()
338 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
357 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_enable()
369 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
380 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
405 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); in hsw_dp_audio_config_update()
419 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); in hsw_dp_audio_config_update()
[all …]
Dintel_ddi.c970 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_hdmi()
992 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_dp()
1014 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_edp()
1294 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
1309 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_active()
1452 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1460 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
1480 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1486 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1495 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Dintel_panel.c537 return intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
544 return intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
553 val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
572 return intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
588 return intel_de_read(dev_priv, in bxt_get_backlight()
606 u32 val = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
616 tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
644 tmp = intel_de_read(dev_priv, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
655 tmp = intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
745 tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Dintel_dpio_phy.c282 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
286 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
291 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
302 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
307 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
319 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
322 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
330 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
342 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
380 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
Dintel_display_power.c354 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
355 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
357 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
358 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
380 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & in hsw_wait_for_power_well_disable()
424 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enable()
436 val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx)); in hsw_power_well_enable()
464 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_disable()
483 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_enable()
488 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); in icl_combo_phy_aux_power_well_enable()
[all …]
Dvlv_dsi_pll.c204 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
218 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
243 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
331 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
349 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
419 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
530 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
553 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
560 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
564 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
Dintel_lvds.c87 val = intel_de_read(dev_priv, lvds_reg); in intel_lvds_port_enabled()
127 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
145 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in intel_lvds_get_config()
158 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
160 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
165 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
169 val = intel_de_read(dev_priv, PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
206 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
315 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
318 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
[all …]
Dintel_dvo.c140 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
155 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
171 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
194 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
198 intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
209 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
216 intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
292 dvo_val = intel_de_read(dev_priv, dvo_reg) & in intel_dvo_pre_enable()
494 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
Dintel_cdclk.c243 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
418 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
423 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
532 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
702 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
707 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
735 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
751 val = intel_de_read(dev_priv, LCPLL_CTL); in bdw_set_cdclk()
759 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
763 val = intel_de_read(dev_priv, LCPLL_CTL); in bdw_set_cdclk()
[all …]
Dintel_display.c525 … intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); in skl_wa_827()
528 … intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); in skl_wa_827()
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); in icl_wa_scalerclkgating()
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); in icl_wa_scalerclkgating()
1057 line1 = intel_de_read(dev_priv, reg) & line_mask; in pipe_scanline_is_moving()
1059 line2 = intel_de_read(dev_priv, reg) & line_mask; in pipe_scanline_is_moving()
1113 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll()
1149 u32 val = intel_de_read(dev_priv, in assert_fdi_tx()
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); in assert_fdi_tx()
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); in assert_fdi_rx()
[all …]
Dintel_fifo_underrun.c98 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
125 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
148 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
179 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
216 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
249 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
Dintel_tv.c909 u32 tmp = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_hw_state()
930 intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
943 intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1098 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_config()
1099 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); in intel_tv_get_config()
1100 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); in intel_tv_get_config()
1101 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); in intel_tv_get_config()
1102 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); in intel_tv_get_config()
1137 tmp = intel_de_read(dev_priv, TV_WIN_POS); in intel_tv_get_config()
1141 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); in intel_tv_get_config()
[all …]
Dintel_crt.c77 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
114 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
462 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
486 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
521 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
537 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
588 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
737 u32 vsync = intel_de_read(dev_priv, vsync_reg); in intel_crt_load_detect()
954 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
1005 adpa = intel_de_read(dev_priv, adpa_reg); in intel_crt_init()
[all …]
Dintel_hdmi.c75 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
84 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
219 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
257 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_read_infoframe()
265 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); in g4x_read_infoframe()
272 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_infoframes_enabled()
293 u32 val = intel_de_read(dev_priv, reg); in ibx_write_infoframe()
333 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); in ibx_read_infoframe()
341 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
350 u32 val = intel_de_read(dev_priv, reg); in ibx_infoframes_enabled()
[all …]
Dintel_display_debugfs.c61 mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; in i915_fbc_status()
63 mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; in i915_fbc_status()
65 mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; in i915_fbc_status()
67 mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK; in i915_fbc_status()
69 mask = intel_de_read(dev_priv, FBC_STATUS) & in i915_fbc_status()
103 reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL); in i915_fbc_false_color_set()
133 if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE) in i915_ips_status()
155 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN; in i915_sr_status()
158 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
160 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; in i915_sr_status()
[all …]
Dintel_overlay.c326 tmp = intel_de_read(dev_priv, DOVSTA); in intel_overlay_continue()
461 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { in intel_overlay_release_old_vid()
909 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); in update_pfit_vscale_ratio()
917 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; in update_pfit_vscale_ratio()
920 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
922 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1261 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); in intel_overlay_attrs_ioctl()
1262 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); in intel_overlay_attrs_ioctl()
1263 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); in intel_overlay_attrs_ioctl()
1264 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); in intel_overlay_attrs_ioctl()
[all …]
Dintel_psr.c135 val = intel_de_read(dev_priv, imr_reg); in psr_irq_control()
208 u32 val = intel_de_read(dev_priv, in intel_psr_irq_handler()
234 val = intel_de_read(dev_priv, imr_reg); in intel_psr_irq_handler()
500 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & in hsw_activate_psr1()
607 val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)); in psr2_program_idle_frames()
873 intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); in intel_psr_activate()
876 intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); in intel_psr_activate()
905 u32 chicken = intel_de_read(dev_priv, reg); in intel_psr_enable_source()
938 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); in intel_psr_enable_source()
981 val = intel_de_read(dev_priv, in intel_psr_enable_locked()
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Dintel_vdsc.c997 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); in intel_dsc_get_config()
998 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); in intel_dsc_get_config()
1000 dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); in intel_dsc_get_config()
1001 dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe)); in intel_dsc_get_config()
1015 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); in intel_dsc_get_config()
1017 val = intel_de_read(dev_priv, in intel_dsc_get_config()
1121 dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg); in intel_dsc_disable()
1126 dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg); in intel_dsc_disable()
Dintel_dp.c262 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_max_source_rate()
803 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
817 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
827 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
984 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
990 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
1007 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
1173 pp_div = intel_de_read(dev_priv, pp_div_reg); in edp_notify_handler()
1197 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
1210 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
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Dintel_hdcp.c115 return intel_de_read(dev_priv, in intel_hdcp_in_use()
123 return intel_de_read(dev_priv, in intel_hdcp2_in_use()
189 val = intel_de_read(dev_priv, HDCP_KEY_STATUS); in intel_hdcp_load_keys()
198 if (!(intel_de_read(dev_priv, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) in intel_hdcp_load_keys()
524 if (!(intel_de_read(dev_priv, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { in intel_hdcp_validate_v_prime()
674 an.reg[0] = intel_de_read(dev_priv, in intel_hdcp_auth()
676 an.reg[1] = intel_de_read(dev_priv, in intel_hdcp_auth()
715 if (wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & in intel_hdcp_auth()
748 if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & in intel_hdcp_auth()
756 intel_de_read(dev_priv, HDCP_STATUS(dev_priv, in intel_hdcp_auth()
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Dintel_dsb.c40 return DSB_STATUS & intel_de_read(i915, DSB_CTRL(pipe, id)); in is_dsb_busy()
48 dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_enable_engine()
66 dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_disable_engine()

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