1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 13 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 14 #define GUC_CLIENT_PRIORITY_HIGH 1 15 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 16 #define GUC_CLIENT_PRIORITY_NORMAL 3 17 #define GUC_CLIENT_PRIORITY_NUM 4 18 19 #define GUC_MAX_STAGE_DESCRIPTORS 1024 20 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 21 22 #define GUC_RENDER_ENGINE 0 23 #define GUC_VIDEO_ENGINE 1 24 #define GUC_BLITTER_ENGINE 2 25 #define GUC_VIDEOENHANCE_ENGINE 3 26 #define GUC_VIDEO_ENGINE2 4 27 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 28 29 #define GUC_MAX_ENGINE_CLASSES 16 30 #define GUC_MAX_INSTANCES_PER_CLASS 32 31 32 #define GUC_DOORBELL_INVALID 256 33 34 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 35 36 /* Work queue item header definitions */ 37 #define WQ_STATUS_ACTIVE 1 38 #define WQ_STATUS_SUSPENDED 2 39 #define WQ_STATUS_CMD_ERROR 3 40 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 41 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 42 #define WQ_TYPE_SHIFT 0 43 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 44 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 45 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 46 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT) 47 #define WQ_TARGET_SHIFT 10 48 #define WQ_LEN_SHIFT 16 49 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 50 #define WQ_PRESENT_WORKLOAD (1 << 28) 51 52 #define WQ_RING_TAIL_SHIFT 20 53 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 54 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 55 56 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 57 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 58 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 59 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 60 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 61 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 62 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 63 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 64 65 #define GUC_CTL_LOG_PARAMS 0 66 #define GUC_LOG_VALID (1 << 0) 67 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 68 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 69 #define GUC_LOG_CRASH_SHIFT 4 70 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 71 #define GUC_LOG_DPC_SHIFT 6 72 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) 73 #define GUC_LOG_ISR_SHIFT 9 74 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) 75 #define GUC_LOG_BUF_ADDR_SHIFT 12 76 77 #define GUC_CTL_WA 1 78 #define GUC_CTL_FEATURE 2 79 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14) 80 81 #define GUC_CTL_DEBUG 3 82 #define GUC_LOG_VERBOSITY_SHIFT 0 83 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 84 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 85 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 86 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 87 /* Verbosity range-check limits, without the shift */ 88 #define GUC_LOG_VERBOSITY_MIN 0 89 #define GUC_LOG_VERBOSITY_MAX 3 90 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 91 #define GUC_LOG_DESTINATION_MASK (3 << 4) 92 #define GUC_LOG_DISABLED (1 << 6) 93 #define GUC_PROFILE_ENABLED (1 << 7) 94 95 #define GUC_CTL_ADS 4 96 #define GUC_ADS_ADDR_SHIFT 1 97 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 98 99 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 100 101 /* Generic GT SysInfo data types */ 102 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0 103 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1 104 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2 105 #define GUC_GENERIC_GT_SYSINFO_MAX 16 106 107 /* 108 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. 109 * Bit 7 can be used for operations that apply to all engine classes&instances. 110 */ 111 #define GUC_ENGINE_CLASS_SHIFT 0 112 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) 113 #define GUC_ENGINE_INSTANCE_SHIFT 3 114 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) 115 #define GUC_ENGINE_ALL_INSTANCES BIT(7) 116 117 #define MAKE_GUC_ID(class, instance) \ 118 (((class) << GUC_ENGINE_CLASS_SHIFT) | \ 119 ((instance) << GUC_ENGINE_INSTANCE_SHIFT)) 120 121 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \ 122 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) 123 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ 124 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) 125 126 /* Work item for submitting workloads into work queue of GuC. */ 127 struct guc_wq_item { 128 u32 header; 129 u32 context_desc; 130 u32 submit_element_info; 131 u32 fence_id; 132 } __packed; 133 134 struct guc_process_desc { 135 u32 stage_id; 136 u64 db_base_addr; 137 u32 head; 138 u32 tail; 139 u32 error_offset; 140 u64 wq_base_addr; 141 u32 wq_size_bytes; 142 u32 wq_status; 143 u32 engine_presence; 144 u32 priority; 145 u32 reserved[30]; 146 } __packed; 147 148 /* engine id and context id is packed into guc_execlist_context.context_id*/ 149 #define GUC_ELC_CTXID_OFFSET 0 150 #define GUC_ELC_ENGINE_OFFSET 29 151 152 /* The execlist context including software and HW information */ 153 struct guc_execlist_context { 154 u32 context_desc; 155 u32 context_id; 156 u32 ring_status; 157 u32 ring_lrca; 158 u32 ring_begin; 159 u32 ring_end; 160 u32 ring_next_free_location; 161 u32 ring_current_tail_pointer_value; 162 u8 engine_state_submit_value; 163 u8 engine_state_wait_value; 164 u16 pagefault_count; 165 u16 engine_submit_queue_count; 166 } __packed; 167 168 /* 169 * This structure describes a stage set arranged for a particular communication 170 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 171 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 172 * to avoid confusion with all the other things already named "context" in the 173 * driver. A static pool of these descriptors are stored inside a GEM object 174 * (stage_desc_pool) which is held for the entire lifetime of our interaction 175 * with the GuC, being allocated before the GuC is loaded with its firmware. 176 */ 177 struct guc_stage_desc { 178 u32 sched_common_area; 179 u32 stage_id; 180 u32 pas_id; 181 u8 engines_used; 182 u64 db_trigger_cpu; 183 u32 db_trigger_uk; 184 u64 db_trigger_phy; 185 u16 db_id; 186 187 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 188 189 u8 attribute; 190 191 u32 priority; 192 193 u32 wq_sampled_tail_offset; 194 u32 wq_total_submit_enqueues; 195 196 u32 process_desc; 197 u32 wq_addr; 198 u32 wq_size; 199 200 u32 engine_presence; 201 202 u8 engine_suspended; 203 204 u8 reserved0[3]; 205 u64 reserved1[1]; 206 207 u64 desc_private; 208 } __packed; 209 210 /** 211 * DOC: CTB based communication 212 * 213 * The CTB (command transport buffer) communication between Host and GuC 214 * is based on u32 data stream written to the shared buffer. One buffer can 215 * be used to transmit data only in one direction (one-directional channel). 216 * 217 * Current status of the each buffer is stored in the buffer descriptor. 218 * Buffer descriptor holds tail and head fields that represents active data 219 * stream. The tail field is updated by the data producer (sender), and head 220 * field is updated by the data consumer (receiver):: 221 * 222 * +------------+ 223 * | DESCRIPTOR | +=================+============+========+ 224 * +============+ | | MESSAGE(s) | | 225 * | address |--------->+=================+============+========+ 226 * +------------+ 227 * | head | ^-----head--------^ 228 * +------------+ 229 * | tail | ^---------tail-----------------^ 230 * +------------+ 231 * | size | ^---------------size--------------------^ 232 * +------------+ 233 * 234 * Each message in data stream starts with the single u32 treated as a header, 235 * followed by optional set of u32 data that makes message specific payload:: 236 * 237 * +------------+---------+---------+---------+ 238 * | MESSAGE | 239 * +------------+---------+---------+---------+ 240 * | msg[0] | [1] | ... | [n-1] | 241 * +------------+---------+---------+---------+ 242 * | MESSAGE | MESSAGE PAYLOAD | 243 * + HEADER +---------+---------+---------+ 244 * | | 0 | ... | n | 245 * +======+=====+=========+=========+=========+ 246 * | 31:16| code| | | | 247 * +------+-----+ | | | 248 * | 15:5|flags| | | | 249 * +------+-----+ | | | 250 * | 4:0| len| | | | 251 * +------+-----+---------+---------+---------+ 252 * 253 * ^-------------len-------------^ 254 * 255 * The message header consists of: 256 * 257 * - **len**, indicates length of the message payload (in u32) 258 * - **code**, indicates message code 259 * - **flags**, holds various bits to control message handling 260 */ 261 262 /* 263 * Describes single command transport buffer. 264 * Used by both guc-master and clients. 265 */ 266 struct guc_ct_buffer_desc { 267 u32 addr; /* gfx address */ 268 u64 host_private; /* host private data */ 269 u32 size; /* size in bytes */ 270 u32 head; /* offset updated by GuC*/ 271 u32 tail; /* offset updated by owner */ 272 u32 is_in_error; /* error indicator */ 273 u32 fence; /* fence updated by GuC */ 274 u32 status; /* status updated by GuC */ 275 u32 owner; /* id of the channel owner */ 276 u32 owner_sub_id; /* owner-defined field for extra tracking */ 277 u32 reserved[5]; 278 } __packed; 279 280 /* Type of command transport buffer */ 281 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 282 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 283 284 /* 285 * Definition of the command transport message header (DW0) 286 * 287 * bit[4..0] message len (in dwords) 288 * bit[7..5] reserved 289 * bit[8] response (G2H only) 290 * bit[8] write fence to desc (H2G only) 291 * bit[9] write status to H2G buff (H2G only) 292 * bit[10] send status back via G2H (H2G only) 293 * bit[15..11] reserved 294 * bit[31..16] action code 295 */ 296 #define GUC_CT_MSG_LEN_SHIFT 0 297 #define GUC_CT_MSG_LEN_MASK 0x1F 298 #define GUC_CT_MSG_IS_RESPONSE (1 << 8) 299 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 300 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 301 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 302 #define GUC_CT_MSG_ACTION_SHIFT 16 303 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 304 305 #define GUC_FORCEWAKE_RENDER (1 << 0) 306 #define GUC_FORCEWAKE_MEDIA (1 << 1) 307 308 #define GUC_POWER_UNSPECIFIED 0 309 #define GUC_POWER_D0 1 310 #define GUC_POWER_D1 2 311 #define GUC_POWER_D2 3 312 #define GUC_POWER_D3 4 313 314 /* Scheduling policy settings */ 315 316 /* Reset engine upon preempt failure */ 317 #define POLICY_RESET_ENGINE (1<<0) 318 /* Preempt to idle on quantum expiry */ 319 #define POLICY_PREEMPT_TO_IDLE (1<<1) 320 321 #define POLICY_MAX_NUM_WI 15 322 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 323 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 324 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 325 #define POLICY_DEFAULT_FAULT_TIME_US 250000 326 327 struct guc_policy { 328 /* Time for one workload to execute. (in micro seconds) */ 329 u32 execution_quantum; 330 /* Time to wait for a preemption request to completed before issuing a 331 * reset. (in micro seconds). */ 332 u32 preemption_time; 333 /* How much time to allow to run after the first fault is observed. 334 * Then preempt afterwards. (in micro seconds) */ 335 u32 fault_time; 336 u32 policy_flags; 337 u32 reserved[8]; 338 } __packed; 339 340 struct guc_policies { 341 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES]; 342 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 343 /* In micro seconds. How much time to allow before DPC processing is 344 * called back via interrupt (to prevent DPC queue drain starving). 345 * Typically 1000s of micro seconds (example only, not granularity). */ 346 u32 dpc_promote_time; 347 348 /* Must be set to take these new values. */ 349 u32 is_valid; 350 351 /* Max number of WIs to process per call. A large value may keep CS 352 * idle. */ 353 u32 max_num_work_items; 354 355 u32 reserved[4]; 356 } __packed; 357 358 /* GuC MMIO reg state struct */ 359 struct guc_mmio_reg { 360 u32 offset; 361 u32 value; 362 u32 flags; 363 #define GUC_REGSET_MASKED (1 << 0) 364 } __packed; 365 366 /* GuC register sets */ 367 struct guc_mmio_reg_set { 368 u32 address; 369 u16 count; 370 u16 reserved; 371 } __packed; 372 373 /* HW info */ 374 struct guc_gt_system_info { 375 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 376 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES]; 377 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX]; 378 } __packed; 379 380 /* Clients info */ 381 struct guc_ct_pool_entry { 382 struct guc_ct_buffer_desc desc; 383 u32 reserved[7]; 384 } __packed; 385 386 #define GUC_CT_POOL_SIZE 2 387 388 struct guc_clients_info { 389 u32 clients_num; 390 u32 reserved0[13]; 391 u32 ct_pool_addr; 392 u32 ct_pool_count; 393 u32 reserved[4]; 394 } __packed; 395 396 /* GuC Additional Data Struct */ 397 struct guc_ads { 398 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 399 u32 reserved0; 400 u32 scheduler_policies; 401 u32 gt_system_info; 402 u32 clients_info; 403 u32 control_data; 404 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 405 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 406 u32 private_data; 407 u32 reserved[15]; 408 } __packed; 409 410 /* GuC logging structures */ 411 412 enum guc_log_buffer_type { 413 GUC_ISR_LOG_BUFFER, 414 GUC_DPC_LOG_BUFFER, 415 GUC_CRASH_DUMP_LOG_BUFFER, 416 GUC_MAX_LOG_BUFFER 417 }; 418 419 /** 420 * struct guc_log_buffer_state - GuC log buffer state 421 * 422 * Below state structure is used for coordination of retrieval of GuC firmware 423 * logs. Separate state is maintained for each log buffer type. 424 * read_ptr points to the location where i915 read last in log buffer and 425 * is read only for GuC firmware. write_ptr is incremented by GuC with number 426 * of bytes written for each log entry and is read only for i915. 427 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 428 * GuC firmware expects that while it is writing to 2nd half of the buffer, 429 * first half would get consumed by Host and then get a flush completed 430 * acknowledgment from Host, so that it does not end up doing any overwrite 431 * causing loss of logs. So when buffer gets half filled & i915 has requested 432 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 433 * to the value of write_ptr and raise the interrupt. 434 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 435 * field and also update read_ptr with the value of sample_write_ptr, before 436 * sending an acknowledgment to GuC. marker & version fields are for internal 437 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 438 * time GuC detects the log buffer overflow. 439 */ 440 struct guc_log_buffer_state { 441 u32 marker[2]; 442 u32 read_ptr; 443 u32 write_ptr; 444 u32 size; 445 u32 sampled_write_ptr; 446 union { 447 struct { 448 u32 flush_to_file:1; 449 u32 buffer_full_cnt:4; 450 u32 reserved:27; 451 }; 452 u32 flags; 453 }; 454 u32 version; 455 } __packed; 456 457 struct guc_ctx_report { 458 u32 report_return_status; 459 u32 reserved1[64]; 460 u32 affected_count; 461 u32 reserved2[2]; 462 } __packed; 463 464 /* GuC Shared Context Data Struct */ 465 struct guc_shared_ctx_data { 466 u32 addr_of_last_preempted_data_low; 467 u32 addr_of_last_preempted_data_high; 468 u32 addr_of_last_preempted_data_high_tmp; 469 u32 padding; 470 u32 is_mapped_to_proxy; 471 u32 proxy_ctx_id; 472 u32 engine_reset_ctx_id; 473 u32 media_reset_count; 474 u32 reserved1[8]; 475 u32 uk_last_ctx_switch_reason; 476 u32 was_reset; 477 u32 lrca_gpu_addr; 478 u64 execlist_ctx; 479 u32 reserved2[66]; 480 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 481 } __packed; 482 483 /** 484 * DOC: MMIO based communication 485 * 486 * The MMIO based communication between Host and GuC uses software scratch 487 * registers, where first register holds data treated as message header, 488 * and other registers are used to hold message payload. 489 * 490 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, 491 * but no H2G command takes more than 8 parameters and the GuC FW 492 * itself uses an 8-element array to store the H2G message. 493 * 494 * +-----------+---------+---------+---------+ 495 * | MMIO[0] | MMIO[1] | ... | MMIO[n] | 496 * +-----------+---------+---------+---------+ 497 * | header | optional payload | 498 * +======+====+=========+=========+=========+ 499 * | 31:28|type| | | | 500 * +------+----+ | | | 501 * | 27:16|data| | | | 502 * +------+----+ | | | 503 * | 15:0|code| | | | 504 * +------+----+---------+---------+---------+ 505 * 506 * The message header consists of: 507 * 508 * - **type**, indicates message type 509 * - **code**, indicates message code, is specific for **type** 510 * - **data**, indicates message data, optional, depends on **code** 511 * 512 * The following message **types** are supported: 513 * 514 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code 515 * must be priovided in **code** field. Optional action specific parameters 516 * can be provided in remaining payload registers or **data** field. 517 * 518 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, 519 * action response status will be provided in **code** field. Optional 520 * response data can be returned in remaining payload registers or **data** 521 * field. 522 */ 523 524 #define GUC_MAX_MMIO_MSG_LEN 8 525 526 #define INTEL_GUC_MSG_TYPE_SHIFT 28 527 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) 528 #define INTEL_GUC_MSG_DATA_SHIFT 16 529 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT) 530 #define INTEL_GUC_MSG_CODE_SHIFT 0 531 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT) 532 533 #define __INTEL_GUC_MSG_GET(T, m) \ 534 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) 535 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m) 536 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m) 537 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m) 538 539 enum intel_guc_msg_type { 540 INTEL_GUC_MSG_TYPE_REQUEST = 0x0, 541 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF, 542 }; 543 544 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \ 545 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T) 546 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m) 547 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m) 548 549 enum intel_guc_action { 550 INTEL_GUC_ACTION_DEFAULT = 0x0, 551 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 552 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 553 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 554 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 555 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 556 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40, 557 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 558 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 559 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 560 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 561 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005, 562 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 563 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 564 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 565 INTEL_GUC_ACTION_LIMIT 566 }; 567 568 enum intel_guc_preempt_options { 569 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 570 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 571 }; 572 573 enum intel_guc_report_status { 574 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0, 575 INTEL_GUC_REPORT_STATUS_ACKED = 0x1, 576 INTEL_GUC_REPORT_STATUS_ERROR = 0x2, 577 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, 578 }; 579 580 enum intel_guc_sleep_state_status { 581 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1, 582 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, 583 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 584 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 585 }; 586 587 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 588 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 589 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 590 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 591 592 enum intel_guc_response_status { 593 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 594 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, 595 }; 596 597 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \ 598 (typecheck(u32, (m)) && \ 599 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \ 600 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \ 601 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT))) 602 603 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 604 enum intel_guc_recv_message { 605 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 606 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 607 }; 608 609 #endif 610