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Searched refs:lane_count (Results 1 – 25 of 49) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
105 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
106 len = intel_dp->lane_count + 1; in intel_dp_set_link_train()
132 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
134 return ret == intel_dp->lane_count; in intel_dp_update_link_train()
141 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
197 link_config[1] = intel_dp->lane_count; in intel_dp_link_training_clock_recovery()
245 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { in intel_dp_link_training_clock_recovery()
366 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
375 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
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Dintel_dpio_phy.c579 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
581 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
589 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
669 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
682 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
690 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
698 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
721 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
735 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
761 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
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Dintel_dp.h47 int link_rate, u8 lane_count,
50 int link_rate, u8 lane_count);
128 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
130 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
Dvlv_dsi.c43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
47 8 * 100), lane_count); in txbyteclkhs()
51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
54 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1083 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1135 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1137 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1139 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1189 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1191 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
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Dintel_combo_phy.c303 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
311 switch (lane_count) { in intel_combo_phy_power_up_lanes()
322 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
329 switch (lane_count) { in intel_combo_phy_power_up_lanes()
339 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
Dvlv_dsi_pll.c44 int lane_count) in dsi_clk_from_pclk() argument
51 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
125 intel_dsi->lane_count); in vlv_dsi_pll_compute()
316 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_get_pclk()
337 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_get_pclk()
467 intel_dsi->lane_count); in bxt_dsi_pll_compute()
Dintel_combo_phy.h18 int lane_count, bool lane_reversal);
Dintel_dp.c413 u8 lane_count) in intel_dp_link_params_valid() argument
424 if (lane_count == 0 || in intel_dp_link_params_valid()
425 lane_count > intel_dp_max_lane_count(intel_dp)) in intel_dp_link_params_valid()
433 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument
440 max_rate = intel_dp_max_data_rate(link_rate, lane_count); in intel_dp_can_link_train_fallback_for_edp()
448 int link_rate, u8 lane_count) in intel_dp_get_link_train_fallback_values() argument
469 lane_count)) { in intel_dp_get_link_train_fallback_values()
475 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
476 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
480 lane_count >> 1)) { in intel_dp_get_link_train_fallback_values()
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Dintel_dpio_phy.h29 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
Dintel_dsi.c16 return intel_dsi->pclk * bpp / intel_dsi->lane_count; in intel_dsi_bitrate()
Dintel_ddi.c1517 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
1738 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
1750 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
2392 width = intel_dp->lane_count; in cnl_ddi_vswing_sequence()
2537 width = intel_dp->lane_count; in icl_combo_phy_ddi_vswing_sequence()
3169 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
3294 crtc_state->lane_count, in intel_ddi_power_up_lanes()
3313 crtc_state->lane_count, is_mst); in tgl_ddi_pre_enable_dp()
3453 crtc_state->lane_count, is_mst); in hsw_ddi_pre_enable_dp()
4075 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
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Dintel_dp_mst.c59 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_compute_link_config()
73 crtc_state->lane_count)); in intel_dp_mst_compute_link_config()
87 crtc_state->lane_count, in intel_dp_mst_compute_link_config()
158 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_dp_mst_compute_config()
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c261 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
263 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
273 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
277 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
289 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
315 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
320 lane_count); in analogix_dp_link_start()
335 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
340 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c166 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
200 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
210 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
326 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
343 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); in dpcd_set_lt_pattern_and_lane_settings()
431 for (lane = 0; lane < src.link_settings.lane_count; lane++) { in update_drive_settings()
493 for (lane = 1; lane < link_training_setting->link_settings.lane_count; in find_max_drive_settings()
551 max_lt_setting->link_settings.lane_count = in find_max_drive_settings()
552 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
557 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
Ddp_panel.h91 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
93 return (lane_count == 1 || in is_lane_count_valid()
94 lane_count == 2 || in is_lane_count_valid()
95 lane_count == 4); in is_lane_count_valid()
Ddp_audio.h21 u32 lane_count; member
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c266 uint8_t lane_count; member
902 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
915 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
917 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
921 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
925 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
933 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
938 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
995 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1012 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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Dmdfld_dsi_dpi.c474 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
489 val = lane_count; in mdfld_dsi_dpi_controller_init()
510 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
527 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
753 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
777 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
791 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
Dmdfld_dsi_output.c420 config->lane_count = 4; in mdfld_dsi_get_default_config()
422 config->lane_count = 2; in mdfld_dsi_get_default_config()
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dparade-ps8622.c55 u32 lane_count; member
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
500 &ps8622->lane_count)) { in ps8622_probe()
501 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
502 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
505 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c202 link->cur_link_settings.lane_count, in dp_link_settings_read()
209 link->verified_link_cap.lane_count, in dp_link_settings_read()
216 link->reported_link_cap.lane_count, in dp_link_settings_read()
223 link->preferred_link_setting.lane_count, in dp_link_settings_read()
314 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
457 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
458 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
464 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
465 link->cur_link_settings.lane_count; in dp_phy_settings_write()
473 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { in dp_phy_settings_write()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.c608 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
622 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in dce60_configure_encoder()
1143 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1182 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1222 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_output()
1261 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_mst_output()
1342 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings()
1347 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_link_encoder.c221 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data()
281 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn20_link_encoder_get_max_link_cap()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c155 cfg->link_settings.lane_count = in dce110_fill_display_configs()
156 stream->link->cur_link_settings.lane_count; in dce110_fill_display_configs()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in enc1_configure_encoder()
981 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_output()
1020 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_mst_output()
1103 cntl.lanes_number = link_settings->link_settings.lane_count; in dcn10_link_encoder_dp_set_lane_settings()
1108 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dcn10_link_encoder_dp_set_lane_settings()

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