Searched refs:m147_pcc (Results 1 – 4 of 4) sorted by relevance
26 m147_pcc->dma_intr = 0x89; /* Ack and enable ints */ in mvme147_intr()53 m147_pcc->dma_bcr = cmd->SCp.this_residual | (1 << 24); in dma_setup()54 m147_pcc->dma_dadr = addr; in dma_setup()55 m147_pcc->dma_cntrl = flags; in dma_setup()64 m147_pcc->dma_cntrl = 0; in dma_stop()119 m147_pcc->scsi_interrupt = 0x10; /* Assert SCSI bus reset */ in mvme147_init()121 m147_pcc->scsi_interrupt = 0x00; /* Negate SCSI bus reset */ in mvme147_init()123 m147_pcc->scsi_interrupt = 0x40; /* Clear bus reset interrupt */ in mvme147_init()125 m147_pcc->scsi_interrupt = 0x09; /* Enable interrupt */ in mvme147_init()127 m147_pcc->dma_cntrl = 0x00; /* ensure DMA is stopped */ in mvme147_init()[all …]
60 m147_pcc->watchdog = 0x0a; /* Clear timer */ in mvme147_reset()61 m147_pcc->watchdog = 0xa5; /* Enable watchdog - 100ms to reset */ in mvme147_reset()119 m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN | in mvme147_timer_int()121 m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR | in mvme147_timer_int()139 m147_pcc->t1_preload = PCC_TIMER_PRELOAD; in mvme147_sched_init()140 m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN | in mvme147_sched_init()142 m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR | in mvme147_sched_init()156 tmp = m147_pcc->t1_cntrl >> 4; in mvme147_read_clk()157 count = m147_pcc->t1_count; in mvme147_read_clk()158 overflow = m147_pcc->t1_cntrl >> 4; in mvme147_read_clk()[all …]
168 m147_pcc->lan_cntrl = 0; /* clear the interrupts (if any) */ in m147lance_open()169 m147_pcc->lan_cntrl = 0x08 | 0x04; /* Enable irq 4 */ in m147lance_open()177 m147_pcc->lan_cntrl = 0x0; /* disable interrupts */ in m147lance_close()
63 #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000) macro