| /kernel/linux/linux-5.10/drivers/usb/mtu3/ |
| D | mtu3_core.c | 75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); in mtu3_ss_func_set()
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); in mtu3_ss_func_set()
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, in mtu3_hs_softconn_set()
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, in mtu3_hs_softconn_set()
156 void __iomem *mbase = mtu->mac_base; in mtu3_intr_status_clear()
174 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0); in mtu3_intr_disable()
176 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0); in mtu3_intr_disable()
183 void __iomem *mbase = mtu->mac_base; in mtu3_intr_enable()
212 void __iomem *mbase = mtu->mac_base; in mtu3_set_speed()
252 void __iomem *mbase = mtu->mac_base; in mtu3_csr_init()
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| D | mtu3_gadget_ep0.c | 82 void __iomem *fifo = mep->mtu->mac_base + U3D_FIFO0; in ep0_write_fifo()
102 void __iomem *fifo = mep->mtu->mac_base + U3D_FIFO0; in ep0_read_fifo()
138 void __iomem *mbase = mtu->mac_base; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
158 void __iomem *mbase = mtu->mac_base; in ep0_do_status_stage()
276 void __iomem *mbase = mtu->mac_base; in handle_test_mode()
326 void __iomem *mbase = mtu->mac_base; in ep0_handle_feature_dev()
443 void __iomem *mbase = mtu->mac_base; in handle_standard_request()
513 void __iomem *mbase = mtu->mac_base; in ep0_rx_state()
596 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_tx_state()
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| D | mtu3_qmu.c | 192 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_resume()
333 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_start()
377 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_stop()
421 void __iomem *mbase = mtu->mac_base; in qmu_tx_zlp_error_handler()
473 void __iomem *mbase = mtu->mac_base; in qmu_done_tx()
513 void __iomem *mbase = mtu->mac_base; in qmu_done_rx()
561 void __iomem *mbase = mtu->mac_base; in qmu_exception_isr()
601 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_isr()
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| D | mtu3_debugfs.c | 81 void __iomem *mbase = mtu->mac_base; in mtu3_link_state_show()
169 mtu3_debugfs_regset(mtu, mtu->mac_base, regs, 7, "ep-regs", parent); in mtu3_debugfs_ep_regset()
411 mtu3_debugfs_regset(mtu, mtu->mac_base, in ssusb_dev_debugfs_init()
415 mtu3_debugfs_regset(mtu, mtu->mac_base, in ssusb_dev_debugfs_init()
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| D | mtu3.h | 247 void __iomem *mac_base; member
328 void __iomem *mac_base; member
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| D | mtu3_dr.c | 44 mtu3_setbits(ssusb->mac_base, U3D_DEVICE_CONTROL, DC_SESSION); in toggle_opstate()
45 mtu3_setbits(ssusb->mac_base, U3D_POWER_MANAGEMENT, SOFT_CONN); in toggle_opstate()
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| D | mtu3_gadget.c | 433 return (int)mtu3_readl(mtu->mac_base, U3D_USB20_FRAME_NUM); in mtu3_gadget_get_frame()
449 mtu3_setbits(mtu->mac_base, U3D_LINK_POWER_CONTROL, UX_EXIT); in mtu3_gadget_wakeup()
451 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); in mtu3_gadget_wakeup()
455 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); in mtu3_gadget_wakeup()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/atheros/ |
| D | ag71xx.c | 363 void __iomem *mac_base; member
408 iowrite32(value, ag->mac_base + reg); in ag71xx_wr()
410 (void)ioread32(ag->mac_base + reg); in ag71xx_wr()
415 return ioread32(ag->mac_base + reg); in ag71xx_rr()
422 r = ag->mac_base + reg; in ag71xx_sb()
432 r = ag->mac_base + reg; in ag71xx_cb()
1911 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); in ag71xx_probe()
1912 if (!ag->mac_base) in ag71xx_probe()
2002 (unsigned long)ag->mac_base, ndev->irq, in ag71xx_probe()
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| /kernel/linux/linux-5.10/drivers/atm/ |
| D | eni.c | 1691 void __iomem *mac_base; in get_esi_fpga() local
1694 mac_base = base+EPROM_SIZE-sizeof(struct midway_eprom); in get_esi_fpga()
1695 for (i = 0; i < ESI_LEN; i++) dev->esi[i] = readb(mac_base+(i^3)); in get_esi_fpga()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 13733 u32 mac_base; in bnx2x_check_half_open_conn() local
13747 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_check_half_open_conn()
13750 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13751 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13754 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) in bnx2x_check_half_open_conn()
13765 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in bnx2x_check_half_open_conn()
13773 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()
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