/kernel/linux/linux-5.10/drivers/clk/mmp/ |
D | clk-frac.c | 38 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_round_rate() 57 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local 64 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate() 67 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate() 74 do_div(rate, num * factor->masks->factor); in clk_factor_recalc_rate() 84 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local 93 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_set_rate() 106 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate() 107 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; in clk_factor_set_rate() 109 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate() [all …]
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/kernel/linux/linux-5.10/drivers/clk/spear/ |
D | clk-aux-synth.c | 80 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate() 81 if (eqn == aux->masks->eq1_mask) in clk_aux_recalc_rate() 85 num = (val >> aux->masks->xscale_sel_shift) & in clk_aux_recalc_rate() 86 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate() 89 den *= (val >> aux->masks->yscale_sel_shift) & in clk_aux_recalc_rate() 90 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate() 114 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate() 115 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << in clk_aux_set_rate() 116 aux->masks->eq_sel_shift; in clk_aux_set_rate() 117 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate() [all …]
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/kernel/linux/linux-5.10/kernel/irq/ |
D | affinity.c | 45 cpumask_var_t *masks; in alloc_node_to_cpumask() local 48 masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL); in alloc_node_to_cpumask() 49 if (!masks) in alloc_node_to_cpumask() 53 if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL)) in alloc_node_to_cpumask() 57 return masks; in alloc_node_to_cpumask() 61 free_cpumask_var(masks[node]); in alloc_node_to_cpumask() 62 kfree(masks); in alloc_node_to_cpumask() 66 static void free_node_to_cpumask(cpumask_var_t *masks) in free_node_to_cpumask() argument 71 free_cpumask_var(masks[node]); in free_node_to_cpumask() 72 kfree(masks); in free_node_to_cpumask() [all …]
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/kernel/linux/linux-5.10/arch/riscv/mm/ |
D | pageattr.c | 19 struct pageattr_masks *masks = walk->private; in set_pageattr_masks() local 22 new_val &= ~(pgprot_val(masks->clear_mask)); in set_pageattr_masks() 23 new_val |= (pgprot_val(masks->set_mask)); in set_pageattr_masks() 113 struct pageattr_masks masks = { in __set_memory() local 123 &masks); in __set_memory() 158 struct pageattr_masks masks = { in set_direct_map_invalid_noflush() local 164 ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); in set_direct_map_invalid_noflush() 175 struct pageattr_masks masks = { in set_direct_map_default_noflush() local 181 ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); in set_direct_map_default_noflush()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_dpp_cm.c | 119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap() 121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap() 214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix() 216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix() 261 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field() 263 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field() 265 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field() 267 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field() 270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field() 272 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; in dpp1_cm_get_reg_field() [all …]
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D | dcn10_cm_common.h | 71 struct xfer_func_mask masks; member 86 struct cm_color_matrix_mask masks; member
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_i2c_hw.c | 41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name 80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) in get_channel_status() 82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) in get_channel_status() 84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) in get_channel_status() 86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status() 280 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) in set_speed() 600 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument 607 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct() 623 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument 630 masks); in dce100_i2c_hw_construct() [all …]
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D | dce_i2c_hw.h | 273 const struct dce_i2c_mask *masks; member 282 const struct dce_i2c_mask *masks); 290 const struct dce_i2c_mask *masks); 298 const struct dce_i2c_mask *masks); 306 const struct dce_i2c_mask *masks); 314 const struct dce_i2c_mask *masks);
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D | dce_hwseq.c | 38 hws->shifts->field_name, hws->masks->field_name 75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock() 129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
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D | dce_audio.h | 142 const struct dce_audio_mask *masks; member 150 const struct dce_audio_mask *masks); 158 const struct dce_audio_mask *masks);
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_dpp_cm.c | 179 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field() 181 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field() 184 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field() 186 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field() 188 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field() 190 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field() 193 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field() 195 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field() 197 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field() 199 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field() [all …]
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D | dcn30_dwb_cm.c | 53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam() 55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam() 58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam() 60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam() 62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam() 64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam() 67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam() 69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam() 71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam() 73 reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam() [all …]
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D | dcn30_mpc.c | 170 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field() 172 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field() 175 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field() 177 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field() 179 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field() 181 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field() 184 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field() 186 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field() 188 reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field() 190 reg->masks.field_region_linear_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in mpc3_ogam_get_reg_field() [all …]
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/kernel/linux/linux-5.10/drivers/clk/uniphier/ |
D | clk-uniphier-mux.c | 17 const unsigned int *masks; member 27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent() 44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent() 77 mux->masks = data->masks; in uniphier_clk_register_mux()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_mpc.c | 166 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc() 168 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc() 224 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default() 226 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default() 252 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field() 254 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field() 256 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field() 258 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field() 260 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field() 262 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field() [all …]
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D | dcn20_dpp_cm.c | 190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap() 192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap() 285 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc() 287 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc() 363 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 365 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field() 367 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 369 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field() 372 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field() 374 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field() [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
D | tdm-slot.txt | 20 tx and rx masks. 22 For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit 24 the masks. 26 The explicit masks are given as array of integers, where the first
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/kernel/linux/linux-5.10/drivers/s390/char/ |
D | sclp.h | 106 u8 masks[4 * 1021]; /* variable length */ member 117 static inline sccb_mask_t sccb_get_mask(u8 *masks, size_t len, int i) in sccb_get_mask() argument 121 memcpy(&res, masks + i * len, min(sizeof(res), len)); in sccb_get_mask() 125 static inline void sccb_set_mask(u8 *masks, size_t len, int i, sccb_mask_t val) in sccb_set_mask() argument 127 memset(masks + i * len, 0, len); in sccb_set_mask() 128 memcpy(masks + i * len, &val, min(sizeof(val), len)); in sccb_set_mask() 135 sccb_get_mask(__sccb->masks, __sccb->mask_length, i); \ 146 sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \
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/kernel/linux/linux-5.10/tools/perf/trace/beauty/ |
D | prctl.c | 65 const u8 masks[] = { in syscall_arg__scnprintf_prctl_option() local 78 if (option < ARRAY_SIZE(masks)) in syscall_arg__scnprintf_prctl_option() 79 arg->mask |= masks[option]; in syscall_arg__scnprintf_prctl_option()
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/kernel/linux/linux-5.10/drivers/gpu/drm/via/ |
D | via_irq.c | 211 maskarray_t *masks; in via_driver_irq_wait() local 234 masks = dev_priv->irq_masks; in via_driver_irq_wait() 237 if (masks[real_irq][2] && !force_sequence) { in via_driver_irq_wait() 239 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == in via_driver_irq_wait() 240 masks[irq][4])); in via_driver_irq_wait()
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/kernel/linux/linux-5.10/net/openvswitch/ |
D | flow_table.c | 261 if (ovsl_dereference(old->masks[i])) in tbl_mask_array_realloc() 262 new->masks[new->count++] = old->masks[i]; in tbl_mask_array_realloc() 292 BUG_ON(ovsl_dereference(ma->masks[ma_count])); in tbl_mask_array_add_mask() 294 rcu_assign_pointer(ma->masks[ma_count], new); in tbl_mask_array_add_mask() 308 if (mask == ovsl_dereference(ma->masks[i])) in tbl_mask_array_del_mask() 318 rcu_assign_pointer(ma->masks[i], ma->masks[ma_count - 1]); in tbl_mask_array_del_mask() 319 RCU_INIT_POINTER(ma->masks[ma_count - 1], NULL); in tbl_mask_array_del_mask() 743 mask = rcu_dereference_ovsl(ma->masks[*index]); in flow_lookup() 761 mask = rcu_dereference_ovsl(ma->masks[i]); in flow_lookup() 882 mask = ovsl_dereference(ma->masks[i]); in ovs_flow_tbl_lookup_exact() [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mux/ |
D | reg-mux.txt | 11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask 21 pair in the mux-reg-masks array. 35 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ 97 mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
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/kernel/linux/linux-5.10/drivers/edac/ |
D | dmc520_edac.c | 173 int masks[NUMBER_OF_IRQS]; member 436 mask = pvt->masks[idx]; in dmc520_isr() 477 int masks[NUMBER_OF_IRQS] = { 0 }; in dmc520_edac_probe() local 494 masks[idx] = dmc520_irq_configs[idx].mask; in dmc520_edac_probe() 533 memcpy(pvt->masks, masks, sizeof(masks)); in dmc520_edac_probe() 622 irq_mask_all |= pvt->masks[idx]; in dmc520_edac_remove()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
D | hw_factory_dcn10.c | 157 generic->masks = &generic_mask[en]; in define_generic_registers() 182 ddc->masks = &ddc_mask; in define_ddc_registers() 192 hpd->masks = &hpd_mask; in define_hpd_registers()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
D | hw_factory_dcn21.c | 165 generic->masks = &generic_mask[en]; in define_generic_registers() 190 ddc->masks = &ddc_mask[en]; in define_ddc_registers() 200 hpd->masks = &hpd_mask; in define_hpd_registers()
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