Searched refs:mcs_offset (Results 1 – 9 of 9) sorted by relevance
76 tmpval = (rtlphy->mcs_offset[0][6]) + in rtl92cu_phy_rf6052_set_cck_txpower()77 (rtlphy->mcs_offset[0][7] << 8); in rtl92cu_phy_rf6052_set_cck_txpower()79 tmpval = (rtlphy->mcs_offset[0][14]) + in rtl92cu_phy_rf6052_set_cck_txpower()80 (rtlphy->mcs_offset[0][15] << 24); in rtl92cu_phy_rf6052_set_cck_txpower()172 writeval = rtlphy->mcs_offset in _rtl92c_get_txpower_writeval_by_regulatory()195 writeval = rtlphy->mcs_offset[chnlgroup][index + in _rtl92c_get_txpower_writeval_by_regulatory()227 pwr_diff_limit[i] = (u8) ((rtlphy->mcs_offset in _rtl92c_get_txpower_writeval_by_regulatory()261 writeval = rtlphy->mcs_offset[chnlgroup] in _rtl92c_get_txpower_writeval_by_regulatory()
73 tmpval = (rtlphy->mcs_offset[0][6]) + in rtl92ce_phy_rf6052_set_cck_txpower()74 (rtlphy->mcs_offset[0][7] << 8); in rtl92ce_phy_rf6052_set_cck_txpower()77 tmpval = (rtlphy->mcs_offset[0][14]) + in rtl92ce_phy_rf6052_set_cck_txpower()78 (rtlphy->mcs_offset[0][15] << 24); in rtl92ce_phy_rf6052_set_cck_txpower()182 writeval = rtlphy->mcs_offset[chnlgroup][index + in _rtl92c_get_txpower_writeval_by_regulatory()212 writeval = rtlphy->mcs_offset[chnlgroup] in _rtl92c_get_txpower_writeval_by_regulatory()247 pwr_diff_limit[i] = (u8) ((rtlphy->mcs_offset in _rtl92c_get_txpower_writeval_by_regulatory()287 writeval = rtlphy->mcs_offset[chnlgroup] in _rtl92c_get_txpower_writeval_by_regulatory()
82 tmpval = (rtlphy->mcs_offset[0][6]) + in rtl92d_phy_rf6052_set_cck_txpower()83 (rtlphy->mcs_offset[0][7] << 8); in rtl92d_phy_rf6052_set_cck_txpower()85 tmpval = (rtlphy->mcs_offset[0][14]) + in rtl92d_phy_rf6052_set_cck_txpower()86 (rtlphy->mcs_offset[0][15] << 24); in rtl92d_phy_rf6052_set_cck_txpower()203 writeval = rtlphy->mcs_offset in _rtl92d_get_txpower_writeval_by_regulatory()223 writeval = rtlphy->mcs_offset in _rtl92d_get_txpower_writeval_by_regulatory()256 pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset in _rtl92d_get_txpower_writeval_by_regulatory()291 writeval = rtlphy->mcs_offset[chnlgroup][index + in _rtl92d_get_txpower_writeval_by_regulatory()
645 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; in _rtl92d_store_pwrindex_diffrate_offset()649 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); in _rtl92d_store_pwrindex_diffrate_offset()
169 writeval = rtlphy->mcs_offset[chnlgroup][index] + in _rtl92s_get_txpower_writeval_byregulatory()198 writeval = rtlphy->mcs_offset[chnlgroup][index] in _rtl92s_get_txpower_writeval_byregulatory()231 pwrdiff_limit[i] = (u8)((rtlphy->mcs_offset in _rtl92s_get_txpower_writeval_byregulatory()269 writeval = rtlphy->mcs_offset[chnlgroup][index] + in _rtl92s_get_txpower_writeval_byregulatory()
668 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; in _rtl92s_store_pwrindex_diffrate_offset()
271 u8 mcs_offset);
1213 const unsigned int mcs_offset = ARRAY_SIZE(rsi_rates); in rsi_mac80211_set_rate_mask() local1224 bm = mask->control[i].legacy | (mask->control[i].ht_mcs[0] << mcs_offset); in rsi_mac80211_set_rate_mask()1228 if (rate_index < mcs_offset) in rsi_mac80211_set_rate_mask()1231 cfg->fixed_hw_rate = rsi_mcsrates[rate_index - mcs_offset]; in rsi_mac80211_set_rate_mask()
1364 u32 mcs_offset[MAX_PG_GROUP][16]; member