/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
D | uvd_v5_0.c | 650 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating() 689 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating() 744 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg() 747 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg() 753 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg() 756 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg() 821 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
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D | uvd_v3_1.c | 209 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm() 225 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm() 603 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg() 606 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg() 612 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg() 615 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
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D | uvd_v4_2.c | 584 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg() 587 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg() 593 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg() 596 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg() 607 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm() 623 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
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D | uvd_v6_0.c | 1310 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating() 1350 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating() 1407 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg() 1410 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg() 1416 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg() 1419 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg() 1489 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
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D | vcn_v1_0.c | 470 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating() 478 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating() 503 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating() 524 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating() 595 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating() 602 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating() 604 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating() 625 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating() 683 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
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D | vcn_v2_0.c | 496 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating() 503 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating() 528 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating() 549 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating() 626 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode() 657 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating() 664 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating() 666 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating() 687 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
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D | vcn_v2_5.c | 560 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating() 567 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating() 595 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating() 616 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating() 694 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode() 725 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating() 732 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating() 734 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating() 754 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
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D | vcn_v3_0.c | 657 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating() 664 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating() 692 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating() 713 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating() 813 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode() 841 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating() 848 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating() 850 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating() 871 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
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D | uvd_v7_0.c | 843 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start() 956 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start() 1585 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1631 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_4_0_d.h | 34 #define mmUVD_CGC_CTRL 0x3D2C macro
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D | uvd_4_2_d.h | 44 #define mmUVD_CGC_CTRL 0x3d2c macro
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D | uvd_3_1_d.h | 44 #define mmUVD_CGC_CTRL 0x3d2c macro
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D | uvd_5_0_d.h | 50 #define mmUVD_CGC_CTRL 0x3d2c macro
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D | uvd_6_0_d.h | 66 #define mmUVD_CGC_CTRL 0x3d2c macro
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D | uvd_7_0_offset.h | 146 #define mmUVD_CGC_CTRL … macro
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
D | vcn_1_0_offset.h | 308 #define mmUVD_CGC_CTRL … macro
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D | vcn_2_5_offset.h | 501 #define mmUVD_CGC_CTRL … macro
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D | vcn_2_0_0_offset.h | 508 #define mmUVD_CGC_CTRL … macro
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D | vcn_3_0_0_offset.h | 817 #define mmUVD_CGC_CTRL … macro
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