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Searched refs:mmUVD_RBC_RB_CNTL (Results 1 – 19 of 19) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h70 #define mmUVD_RBC_RB_CNTL 0x3DA9 macro
Duvd_4_2_d.h74 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_3_1_d.h76 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_5_0_d.h80 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_6_0_d.h96 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_7_0_offset.h204 #define mmUVD_RBC_RB_CNTL macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c410 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v3_1_start()
431 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
448 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v3_1_stop()
Duvd_v4_2.c346 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_start()
367 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
384 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_stop()
Duvd_v5_0.c399 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v5_0_start()
419 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
434 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v5_0_stop()
Duvd_v7_0.c896 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in uvd_v7_0_sriov_start()
1067 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); in uvd_v7_0_start()
1089 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, in uvd_v7_0_start()
1124 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v7_0_stop()
Dvcn_v1_0.c916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start_spg_mode()
940 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start_spg_mode()
1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start_dpg_mode()
1098 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c894 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start_dpg_mode()
1066 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start()
1972 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_0_start_sriov()
Dvcn_v2_5.c877 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start_dpg_mode()
1069 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start()
1289 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_5_sriov_start()
Duvd_v6_0.c821 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v6_0_start()
872 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v6_0_stop()
Dvcn_v3_0.c1005 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start_dpg_mode()
1183 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start()
1362 mmUVD_RBC_RB_CNTL), in vcn_v3_0_start_sriov()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h390 #define mmUVD_RBC_RB_CNTL macro
Dvcn_2_5_offset.h785 #define mmUVD_RBC_RB_CNTL macro
Dvcn_2_0_0_offset.h690 #define mmUVD_RBC_RB_CNTL macro
Dvcn_3_0_0_offset.h1169 #define mmUVD_RBC_RB_CNTL macro