Searched refs:nv_entries (Results 1 – 3 of 3) sorted by relevance
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()119 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_build_wm_range_table()121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_build_wm_range_table()124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn3_build_wm_range_table()[all …]
193 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; member
2227 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_calculate_wm_and_dlg()2232 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.… in dcn30_calculate_wm_and_dlg()2233 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg()2234 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_calculate_wm_and_dlg()2274 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_calculate_wm_and_dlg()2289 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg()2290 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn30_calculate_wm_and_dlg()2314 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_calculate_wm_and_dlg()2315 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.… in dcn30_calculate_wm_and_dlg()2316 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg()[all …]