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Searched refs:nvkm_wr32 (Results 1 – 25 of 207) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv40.c105 nvkm_wr32(device, 0x400720, 0x00000000); in nv40_gr_chan_fini()
106 nvkm_wr32(device, 0x400784, inst); in nv40_gr_chan_fini()
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
[all …]
Dnv20.c42 nvkm_wr32(device, 0x400784, inst >> 4); in nv20_gr_chan_fini()
43 nvkm_wr32(device, 0x400788, 0x00000002); in nv20_gr_chan_fini()
48 nvkm_wr32(device, 0x400144, 0x10000000); in nv20_gr_chan_fini()
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile()
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile()
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile()
163 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); in nv20_gr_tile()
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile()
165 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); in nv20_gr_tile()
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile()
[all …]
Dnv30.c109 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, in nv30_gr_init()
112 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv30_gr_init()
113 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv30_gr_init()
115 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv30_gr_init()
116 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv30_gr_init()
117 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv30_gr_init()
118 nvkm_wr32(device, 0x400890, 0x01b463ff); in nv30_gr_init()
119 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); in nv30_gr_init()
120 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv30_gr_init()
121 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); in nv30_gr_init()
[all …]
Dnv50.c315 nvkm_wr32(device, addr + 0x10, mp10); in nv50_gr_mp_trap()
316 nvkm_wr32(device, addr + 0x14, 0); in nv50_gr_mp_trap()
387 nvkm_wr32(device, ustatus_addr, 0xc0000000); in nv50_gr_tp_trap()
418 nvkm_wr32(device, 0x400500, 0x00000000); in nv50_gr_trap_handler()
443 nvkm_wr32(device, 0x400808, 0); in nv50_gr_trap_handler()
444 nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3); in nv50_gr_trap_handler()
445 nvkm_wr32(device, 0x400848, 0); in nv50_gr_trap_handler()
468 nvkm_wr32(device, 0x40084c, 0); in nv50_gr_trap_handler()
477 nvkm_wr32(device, 0x400804, 0xc0000000); in nv50_gr_trap_handler()
478 nvkm_wr32(device, 0x400108, 0x001); in nv50_gr_trap_handler()
[all …]
Dnv44.c44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
61 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
[all …]
Dnv10.c417 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
425 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
427 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
464 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv17_gr_mthd_lma_window()
465 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv17_gr_mthd_lma_window()
466 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv17_gr_mthd_lma_window()
468 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
470 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
472 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv17_gr_mthd_lma_window()
474 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
[all …]
Dgf100.c53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
106 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
[all …]
Dtu102.c30 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); in tu102_gr_init_fecs_exceptions()
43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
65 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); in tu102_gr_init_zcull()
69 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
71 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
73 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
76 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); in tu102_gr_init_zcull()
84 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff); in tu102_gr_init_gpc_mmu()
85 nvkm_wr32(device, 0x418890, 0x00000000); in tu102_gr_init_gpc_mmu()
86 nvkm_wr32(device, 0x418894, 0x00000000); in tu102_gr_init_gpc_mmu()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv04.c58 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
78 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_pause()
80 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); in nv04_fifo_pause()
92 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); in nv04_fifo_start()
119 nvkm_wr32(device, 0x003280, (engine &= ~mask)); in nv04_fifo_swmthd()
172 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); in nv04_fifo_cache_error()
173 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_cache_error()
175 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
177 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_cache_error()
178 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
[all …]
Dnv40.c70 nvkm_wr32(device, 0x002040, 0x000000ff); in nv40_fifo_init()
71 nvkm_wr32(device, 0x002044, 0x2101ffff); in nv40_fifo_init()
72 nvkm_wr32(device, 0x002058, 0x00000001); in nv40_fifo_init()
74 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv40_fifo_init()
77 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv40_fifo_init()
83 nvkm_wr32(device, 0x002230, 0x00000001); in nv40_fifo_init()
91 nvkm_wr32(device, 0x002220, 0x00030002); in nv40_fifo_init()
94 nvkm_wr32(device, 0x002230, 0x00000000); in nv40_fifo_init()
95 nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 + in nv40_fifo_init()
101 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); in nv40_fifo_init()
[all …]
Dnv17.c60 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); in nv17_fifo_init()
61 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv17_fifo_init()
63 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv17_fifo_init()
66 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv17_fifo_init()
67 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | in nv17_fifo_init()
70 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); in nv17_fifo_init()
72 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); in nv17_fifo_init()
73 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv17_fifo_init()
75 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv17_fifo_init()
76 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
[all …]
Dnv50.c46 nvkm_wr32(device, 0x0032f4, nvkm_memory_addr(cur) >> 12); in nv50_fifo_runlist_update_locked()
47 nvkm_wr32(device, 0x0032ec, p); in nv50_fifo_runlist_update_locked()
48 nvkm_wr32(device, 0x002500, 0x00000101); in nv50_fifo_runlist_update_locked()
84 nvkm_wr32(device, 0x00250c, 0x6f3cfc34); in nv50_fifo_init()
85 nvkm_wr32(device, 0x002044, 0x01003fff); in nv50_fifo_init()
87 nvkm_wr32(device, 0x002100, 0xffffffff); in nv50_fifo_init()
88 nvkm_wr32(device, 0x002140, 0xbfffffff); in nv50_fifo_init()
91 nvkm_wr32(device, 0x002600 + (i * 4), 0x00000000); in nv50_fifo_init()
94 nvkm_wr32(device, 0x003200, 0x00000001); in nv50_fifo_init()
95 nvkm_wr32(device, 0x003250, 0x00000001); in nv50_fifo_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dtu102.c51 nvkm_wr32(device, 0x640008, tmp); in tu102_disp_init()
57 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); in tu102_disp_init()
66 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); in tu102_disp_init()
71 nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp); in tu102_disp_init()
88 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); in tu102_disp_init()
101 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); in tu102_disp_init()
102 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); in tu102_disp_init()
105 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ in tu102_disp_init()
106 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ in tu102_disp_init()
109 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | in tu102_disp_init()
[all …]
Dhdmigv100.c51 nvkm_wr32(device, 0x6f0008 + hdmi, avi_infoframe.header); in gv100_hdmi_ctrl()
52 nvkm_wr32(device, 0x6f000c + hdmi, avi_infoframe.subpack0_low); in gv100_hdmi_ctrl()
53 nvkm_wr32(device, 0x6f0010 + hdmi, avi_infoframe.subpack0_high); in gv100_hdmi_ctrl()
54 nvkm_wr32(device, 0x6f0014 + hdmi, avi_infoframe.subpack1_low); in gv100_hdmi_ctrl()
55 nvkm_wr32(device, 0x6f0018 + hdmi, avi_infoframe.subpack1_high); in gv100_hdmi_ctrl()
62 nvkm_wr32(device, 0x6f0108 + hdmi, vendor_infoframe.header); in gv100_hdmi_ctrl()
63 nvkm_wr32(device, 0x6f010c + hdmi, vendor_infoframe.subpack0_low); in gv100_hdmi_ctrl()
64 nvkm_wr32(device, 0x6f0110 + hdmi, vendor_infoframe.subpack0_high); in gv100_hdmi_ctrl()
65 nvkm_wr32(device, 0x6f0114 + hdmi, 0x00000000); in gv100_hdmi_ctrl()
66 nvkm_wr32(device, 0x6f0118 + hdmi, 0x00000000); in gv100_hdmi_ctrl()
[all …]
Dgv100.c92 nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000); in gv100_disp_super()
93 nvkm_wr32(device, 0x6107a8, 0x80000000); in gv100_disp_super()
135 nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000); in gv100_disp_exception()
148 nvkm_wr32(device, 0x611860, disp->super); in gv100_disp_intr_ctrl_disp()
169 nvkm_wr32(device, 0x611858, wndws); in gv100_disp_intr_ctrl_disp()
170 nvkm_wr32(device, 0x61185c, other); in gv100_disp_intr_ctrl_disp()
196 nvkm_wr32(device, 0x611854, 0x00000001); in gv100_disp_intr_exc_other()
203 nvkm_wr32(device, 0x611854, 0x00010000 << head); in gv100_disp_intr_exc_other()
211 nvkm_wr32(device, 0x611854, stat); in gv100_disp_intr_exc_other()
224 nvkm_wr32(device, 0x611850, BIT(wndw)); in gv100_disp_intr_exc_winim()
[all …]
Dhdmigt215.c53 nvkm_wr32(device, 0x61c528 + soff, avi_infoframe.header); in gt215_hdmi_ctrl()
54 nvkm_wr32(device, 0x61c52c + soff, avi_infoframe.subpack0_low); in gt215_hdmi_ctrl()
55 nvkm_wr32(device, 0x61c530 + soff, avi_infoframe.subpack0_high); in gt215_hdmi_ctrl()
56 nvkm_wr32(device, 0x61c534 + soff, avi_infoframe.subpack1_low); in gt215_hdmi_ctrl()
57 nvkm_wr32(device, 0x61c538 + soff, avi_infoframe.subpack1_high); in gt215_hdmi_ctrl()
63 nvkm_wr32(device, 0x61c508 + soff, 0x000a0184); in gt215_hdmi_ctrl()
64 nvkm_wr32(device, 0x61c50c + soff, 0x00000071); in gt215_hdmi_ctrl()
65 nvkm_wr32(device, 0x61c510 + soff, 0x00000000); in gt215_hdmi_ctrl()
71 nvkm_wr32(device, 0x61c544 + soff, vendor_infoframe.header); in gt215_hdmi_ctrl()
72 nvkm_wr32(device, 0x61c548 + soff, vendor_infoframe.subpack0_low); in gt215_hdmi_ctrl()
[all …]
Dhdmig84.c53 nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header); in g84_hdmi_ctrl()
54 nvkm_wr32(device, 0x61652c + hoff, avi_infoframe.subpack0_low); in g84_hdmi_ctrl()
55 nvkm_wr32(device, 0x616530 + hoff, avi_infoframe.subpack0_high); in g84_hdmi_ctrl()
56 nvkm_wr32(device, 0x616534 + hoff, avi_infoframe.subpack1_low); in g84_hdmi_ctrl()
57 nvkm_wr32(device, 0x616538 + hoff, avi_infoframe.subpack1_high); in g84_hdmi_ctrl()
63 nvkm_wr32(device, 0x616508 + hoff, 0x000a0184); in g84_hdmi_ctrl()
64 nvkm_wr32(device, 0x61650c + hoff, 0x00000071); in g84_hdmi_ctrl()
65 nvkm_wr32(device, 0x616510 + hoff, 0x00000000); in g84_hdmi_ctrl()
71 nvkm_wr32(device, 0x616544 + hoff, vendor_infoframe.header); in g84_hdmi_ctrl()
72 nvkm_wr32(device, 0x616548 + hoff, vendor_infoframe.subpack0_low); in g84_hdmi_ctrl()
[all …]
Dhdmigk104.c53 nvkm_wr32(device, 0x690008 + hdmi, avi_infoframe.header); in gk104_hdmi_ctrl()
54 nvkm_wr32(device, 0x69000c + hdmi, avi_infoframe.subpack0_low); in gk104_hdmi_ctrl()
55 nvkm_wr32(device, 0x690010 + hdmi, avi_infoframe.subpack0_high); in gk104_hdmi_ctrl()
56 nvkm_wr32(device, 0x690014 + hdmi, avi_infoframe.subpack1_low); in gk104_hdmi_ctrl()
57 nvkm_wr32(device, 0x690018 + hdmi, avi_infoframe.subpack1_high); in gk104_hdmi_ctrl()
64 nvkm_wr32(device, 0x690108 + hdmi, vendor_infoframe.header); in gk104_hdmi_ctrl()
65 nvkm_wr32(device, 0x69010c + hdmi, vendor_infoframe.subpack0_low); in gk104_hdmi_ctrl()
66 nvkm_wr32(device, 0x690110 + hdmi, vendor_infoframe.subpack0_high); in gk104_hdmi_ctrl()
74 nvkm_wr32(device, 0x6900cc + hdmi, 0x00000010); in gk104_hdmi_ctrl()
78 nvkm_wr32(device, 0x690080 + hdmi, 0x82000000); in gk104_hdmi_ctrl()
Dhdmigf119.c52 nvkm_wr32(device, 0x61671c + hoff, avi_infoframe.header); in gf119_hdmi_ctrl()
53 nvkm_wr32(device, 0x616720 + hoff, avi_infoframe.subpack0_low); in gf119_hdmi_ctrl()
54 nvkm_wr32(device, 0x616724 + hoff, avi_infoframe.subpack0_high); in gf119_hdmi_ctrl()
55 nvkm_wr32(device, 0x616728 + hoff, avi_infoframe.subpack1_low); in gf119_hdmi_ctrl()
56 nvkm_wr32(device, 0x61672c + hoff, avi_infoframe.subpack1_high); in gf119_hdmi_ctrl()
68 nvkm_wr32(device, 0x616738 + hoff, vendor_infoframe.header); in gf119_hdmi_ctrl()
69 nvkm_wr32(device, 0x61673c + hoff, vendor_infoframe.subpack0_low); in gf119_hdmi_ctrl()
70 nvkm_wr32(device, 0x616740 + hoff, vendor_infoframe.subpack0_high); in gf119_hdmi_ctrl()
77 nvkm_wr32(device, 0x6167ac + hoff, 0x00000010); in gf119_hdmi_ctrl()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgt215.c60 nvkm_wr32(device, 0x10a580, 0x00000001); in gt215_pmu_send()
64 nvkm_wr32(device, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + in gt215_pmu_send()
66 nvkm_wr32(device, 0x10a1c4, process); in gt215_pmu_send()
67 nvkm_wr32(device, 0x10a1c4, message); in gt215_pmu_send()
68 nvkm_wr32(device, 0x10a1c4, data0); in gt215_pmu_send()
69 nvkm_wr32(device, 0x10a1c4, data1); in gt215_pmu_send()
70 nvkm_wr32(device, 0x10a4a0, (addr + 1) & 0x0f); in gt215_pmu_send()
73 nvkm_wr32(device, 0x10a580, 0x00000000); in gt215_pmu_send()
100 nvkm_wr32(device, 0x10a580, 0x00000002); in gt215_pmu_recv()
104 nvkm_wr32(device, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + in gt215_pmu_recv()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c74 nvkm_wr32(device, 0x00b308, 0x00000100); in nv50_mpeg_intr()
84 nvkm_wr32(device, 0x00b100, stat); in nv50_mpeg_intr()
85 nvkm_wr32(device, 0x00b230, 0x00000001); in nv50_mpeg_intr()
94 nvkm_wr32(device, 0x00b32c, 0x00000000); in nv50_mpeg_init()
95 nvkm_wr32(device, 0x00b314, 0x00000100); in nv50_mpeg_init()
96 nvkm_wr32(device, 0x00b0e0, 0x0000001a); in nv50_mpeg_init()
98 nvkm_wr32(device, 0x00b220, 0x00000044); in nv50_mpeg_init()
99 nvkm_wr32(device, 0x00b300, 0x00801ec1); in nv50_mpeg_init()
100 nvkm_wr32(device, 0x00b390, 0x00000000); in nv50_mpeg_init()
101 nvkm_wr32(device, 0x00b394, 0x00000000); in nv50_mpeg_init()
[all …]
Dnv31.c119 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile()
120 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile()
121 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile()
147 nvkm_wr32(device, 0x00b334, base); in nv31_mpeg_mthd_dma()
148 nvkm_wr32(device, 0x00b324, size); in nv31_mpeg_mthd_dma()
154 nvkm_wr32(device, 0x00b360, base); in nv31_mpeg_mthd_dma()
155 nvkm_wr32(device, 0x00b364, size); in nv31_mpeg_mthd_dma()
161 nvkm_wr32(device, 0x00b370, base); in nv31_mpeg_mthd_dma()
162 nvkm_wr32(device, 0x00b374, size); in nv31_mpeg_mthd_dma()
211 nvkm_wr32(device, 0x00b100, stat); in nv31_mpeg_intr()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/
Dfalcon.c76 nvkm_wr32(device, base + 0x004, 0x00000040); in nvkm_falcon_intr()
83 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_intr()
89 nvkm_wr32(device, base + 0x004, intr); in nvkm_falcon_intr()
113 nvkm_wr32(device, base + 0x014, 0xffffffff); in nvkm_falcon_fini()
183 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_init()
187 nvkm_wr32(device, base + 0x014, 0xffffffff); in nvkm_falcon_init()
266 nvkm_wr32(device, base + 0x618, 0x04000000); in nvkm_falcon_init()
268 nvkm_wr32(device, base + 0x618, 0x00000114); in nvkm_falcon_init()
269 nvkm_wr32(device, base + 0x11c, 0); in nvkm_falcon_init()
270 nvkm_wr32(device, base + 0x110, addr >> 8); in nvkm_falcon_init()
[all …]
Dxtensa.c70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
85 nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */ in nvkm_xtensa_fini()
86 nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */ in nvkm_xtensa_fini()
140 nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */ in nvkm_xtensa_init()
141 nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */ in nvkm_xtensa_init()
143 nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */ in nvkm_xtensa_init()
144 nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ in nvkm_xtensa_init()
145 nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ in nvkm_xtensa_init()
147 nvkm_wr32(device, base + 0xcc0, addr >> 8); /* XT_REGION_BASE */ in nvkm_xtensa_init()
148 nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */ in nvkm_xtensa_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c159 nvkm_wr32(device, 0x001584, in setPLL_single()
166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
169 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); in setPLL_single()
178 nvkm_wr32(device, reg, pll); in setPLL_single()
181 nvkm_wr32(device, 0x001584, saved_powerctrl_1); in setPLL_single()
238 nvkm_wr32(device, 0x001584, in setPLL_double_highregs()
259 nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040)); in setPLL_double_highregs()
263 nvkm_wr32(device, 0x680580, ramdac580); in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
[all …]

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