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Searched refs:phy_read (Results 1 – 25 of 90) sorted by relevance

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/kernel/linux/linux-5.10/drivers/net/ethernet/ibm/emac/
Dphy.c32 #define phy_read _phy_read macro
60 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
68 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
120 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
129 adv = phy_read(phy, MII_ADVERTISE); in genmii_setup_aneg()
150 adv = phy_read(phy, MII_CTRL1000); in genmii_setup_aneg()
162 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
178 ctl = phy_read(phy, MII_BMCR); in genmii_setup_forced()
211 phy_read(phy, MII_BMSR); in genmii_poll_link()
212 status = phy_read(phy, MII_BMSR); in genmii_poll_link()
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dlxt.c63 err = phy_read(phydev, MII_BMSR); in lxt970_ack_interrupt()
68 err = phy_read(phydev, MII_LXT970_ISR); in lxt970_ack_interrupt()
92 int err = phy_read(phydev, MII_LXT971_ISR); in lxt971_ack_interrupt()
120 status = phy_read(phydev, MII_BMSR); in lxt973a2_update_link()
125 control = phy_read(phydev, MII_BMCR); in lxt973a2_update_link()
131 status = phy_read(phydev, MII_BMSR); in lxt973a2_update_link()
159 adv = phy_read(phydev, MII_ADVERTISE); in lxt973a2_read_status()
165 lpa = phy_read(phydev, MII_LPA); in lxt973a2_read_status()
208 int val = phy_read(phydev, MII_LXT973_PCR); in lxt973_probe()
215 val = phy_read(phydev, MII_BMCR); in lxt973_probe()
Dbcm87xx.c61 val = phy_read(phydev, regnum); in bcm87xx_of_reg_init()
107 rx_signal_detect = phy_read(phydev, BCM87XX_PMD_RX_SIGNAL_DETECT); in bcm87xx_read_status()
114 pcs_status = phy_read(phydev, BCM87XX_10GBASER_PCS_STATUS); in bcm87xx_read_status()
121 xgxs_lane_status = phy_read(phydev, BCM87XX_XGXS_LANE_STATUS); in bcm87xx_read_status()
142 reg = phy_read(phydev, BCM87XX_LASI_CONTROL); in bcm87xx_config_intr()
160 reg = phy_read(phydev, BCM87XX_LASI_STATUS); in bcm87xx_did_interrupt()
Ddp83tc811.c82 err = phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_ack_interrupt()
86 err = phy_read(phydev, MII_DP83811_INT_STAT2); in dp83811_ack_interrupt()
90 err = phy_read(phydev, MII_DP83811_INT_STAT3); in dp83811_ack_interrupt()
143 phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_set_wol()
200 misr_status = phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_config_intr()
217 misr_status = phy_read(phydev, MII_DP83811_INT_STAT2); in dp83811_config_intr()
232 misr_status = phy_read(phydev, MII_DP83811_INT_STAT3); in dp83811_config_intr()
262 value = phy_read(phydev, MII_DP83811_SGMII_CTRL); in dp83811_config_aneg()
283 value = phy_read(phydev, MII_DP83811_SGMII_CTRL); in dp83811_config_init()
Dat803x.c173 return phy_read(phydev, AT803X_DEBUG_DATA); in at803x_debug_reg_read()
221 context->bmcr = phy_read(phydev, MII_BMCR); in at803x_context_save()
222 context->advertise = phy_read(phydev, MII_ADVERTISE); in at803x_context_save()
223 context->control1000 = phy_read(phydev, MII_CTRL1000); in at803x_context_save()
224 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); in at803x_context_save()
225 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); in at803x_context_save()
226 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); in at803x_context_save()
267 value = phy_read(phydev, AT803X_INTR_ENABLE); in at803x_set_wol()
272 value = phy_read(phydev, AT803X_INTR_STATUS); in at803x_set_wol()
274 value = phy_read(phydev, AT803X_INTR_ENABLE); in at803x_set_wol()
[all …]
Dste10Xp.c35 value = phy_read(phydev, MII_BMCR); in ste10Xp_config_init()
45 value = phy_read(phydev, MII_BMCR); in ste10Xp_config_init()
60 value = phy_read(phydev, MII_XCIIS); in ste10Xp_config_intr()
72 int err = phy_read(phydev, MII_XCIIS); in ste10Xp_ack_interrupt()
Dsmsc.c70 int rc = phy_read (phydev, MII_LAN83C185_ISF); in smsc_phy_ack_interrupt()
83 rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS); in smsc_phy_config_init()
99 int rc = phy_read(phydev, MII_LAN83C185_SPECIAL_MODES); in smsc_phy_reset()
141 rc = phy_read(phydev, SPECIAL_CTRL_STS); in lan87xx_config_aneg()
163 rc = phy_read(phydev, PHY_EDPD_CONFIG); in lan95xx_config_aneg_ext()
189 int rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS); in lan87xx_read_status()
201 read_poll_timeout(phy_read, rc, in lan87xx_read_status()
209 rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS); in lan87xx_read_status()
243 val = phy_read(phydev, stat.reg); in smsc_get_stat()
Dicplus.c124 bmcr = phy_read(phydev, MII_BMCR); in ip1xx_reset()
133 bmcr = phy_read(phydev, MII_BMCR); in ip1xx_reset()
150 c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2); in ip1001_config_init()
160 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); in ip1001_config_init()
269 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); in ip101a_g_config_init()
290 int val = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); in ip101a_g_did_interrupt()
302 int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); in ip101a_g_ack_interrupt()
Dqsemi.c78 err = phy_read(phydev, MII_QS6612_ISR); in qs6612_ack_interrupt()
83 err = phy_read(phydev, MII_BMSR); in qs6612_ack_interrupt()
88 err = phy_read(phydev, MII_EXPANSION); in qs6612_ack_interrupt()
Dnxp-tja11xx.c132 ret = phy_read(phydev, MII_ECTRL); in tja11xx_wakeup()
295 ret = phy_read(phydev, MII_INTSRC); in tja11xx_config_init()
313 ret = phy_read(phydev, MII_CFG1); in tja11xx_read_status()
323 ret = phy_read(phydev, MII_COMMSTAT); in tja11xx_read_status()
338 ret = phy_read(phydev, MII_COMMSTAT); in tja11xx_get_sqi()
371 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); in tja11xx_get_stats()
389 ret = phy_read(phydev, MII_INTSRC); in tja11xx_hwmon_read()
398 ret = phy_read(phydev, MII_INTSRC); in tja11xx_hwmon_read()
565 ret = phy_read(phydev, MII_PHYSID2); in tja1102_match_phy_device()
592 ret = phy_read(phydev, MII_INTSRC); in tja11xx_ack_interrupt()
[all …]
Det1011c.c50 ctl = phy_read(phydev, MII_BMCR); in et1011c_config_aneg()
70 val = phy_read(phydev, ET1011C_STATUS_REG); in et1011c_read_status()
73 val = phy_read(phydev, ET1011C_CONFIG_REG); in et1011c_read_status()
Ddp83822.c126 err = phy_read(phydev, MII_DP83822_MISR1); in dp83822_ack_interrupt()
130 err = phy_read(phydev, MII_DP83822_MISR2); in dp83822_ack_interrupt()
183 phy_read(phydev, MII_DP83822_MISR2); in dp83822_set_wol()
242 misr_status = phy_read(phydev, MII_DP83822_MISR1); in dp83822_config_intr()
260 misr_status = phy_read(phydev, MII_DP83822_MISR2); in dp83822_config_intr()
278 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); in dp83822_config_intr()
293 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); in dp83822_config_intr()
313 int status = phy_read(phydev, MII_DP83822_PHYSTS); in dp83822_read_status()
322 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); in dp83822_read_status()
413 bmcr = phy_read(phydev, MII_BMCR); in dp83822_config_init()
DuPD60620.c40 phy_state = phy_read(phydev, MII_BMSR); in upd60620_read_status()
50 phy_state = phy_read(phydev, PHY_PHYSCR); in upd60620_read_status()
64 phy_state = phy_read(phydev, MII_LPA); in upd60620_read_status()
Ddp83848.c42 int err = phy_read(phydev, DP83848_MISR); in dp83848_ack_interrupt()
51 control = phy_read(phydev, DP83848_MICR); in dp83848_config_intr()
76 val = phy_read(phydev, MII_BMCR); in dp83848_config_init()
Dmicrochip_t1.c64 rc = phy_read(phydev, offset); in access_ereg()
84 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA); in access_ereg()
190 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); in lan87xx_phy_config_intr()
201 int rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); in lan87xx_phy_ack_interrupt()
Dmeson-gxl.c88 ret = phy_read(phydev, TSTREAD1); in meson_gxl_read_reg()
174 lpa = phy_read(phydev, MII_LPA); in meson_gxl_read_status()
178 exp = phy_read(phydev, MII_EXPANSION); in meson_gxl_read_status()
196 int ret = phy_read(phydev, INTSRC_FLAG); in meson_gxl_ack_interrupt()
Dnational.c57 return phy_read(phydev, NS_EXP_MEM_DATA); in ns_exp_read()
81 int ret = phy_read(phydev, DP83865_INT_STATUS); in ns_ack_interrupt()
94 int bmcr = phy_read(phydev, MII_BMCR); in ns_giga_speed_fallback()
Dadin.c295 val = phy_read(phydev, ADIN1300_PHY_CTRL2); in adin_get_downshift()
299 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3); in adin_get_downshift()
340 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2); in adin_get_edpd()
441 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG); in adin_phy_ack_intr()
537 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); in adin_config_mdix()
571 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); in adin_mdix_update()
592 reg = phy_read(phydev, ADIN1300_PHY_STATUS1); in adin_mdix_update()
689 ret = phy_read(phydev, stat->reg1); in adin_get_stat()
706 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT); in adin_get_stats()
Damd.c31 err = phy_read(phydev, MII_BMSR); in am79c_ack_interrupt()
35 err = phy_read(phydev, MII_AM79C_IR); in am79c_ack_interrupt()
Dvitesse.c83 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1); in vsc824x_add_skew()
157 rev = phy_read(phydev, MII_PHYSID2); in vsc738x_config_init()
252 ret = phy_read(phydev, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
282 err = phy_read(phydev, MII_VSC8244_ISTAT); in vsc824x_ack_interrupt()
303 err = phy_read(phydev, MII_VSC8244_ISTAT); in vsc82xx_config_intr()
Dbcm63xx.c24 reg = phy_read(phydev, MII_BCM63XX_IR); in bcm63xx_config_intr()
44 reg = phy_read(phydev, MII_BCM63XX_IR); in bcm63xx_config_init()
Dbroadcom.c78 val = phy_read(phydev, MII_CTRL1000); in bcm54210e_config_init()
318 reg = phy_read(phydev, MII_BCM54XX_ECR); in bcm54xx_config_init()
610 val = phy_read(phydev, reg); in brcm_phy_setbits()
642 err = phy_read(phydev, MII_BMCR); in brcm_fet_config_init()
646 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_config_init()
662 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); in brcm_fet_config_init()
673 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); in brcm_fet_config_init()
712 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_ack_interrupt()
723 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_config_intr()
Dmicrel.c145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); in kszphy_extended_read()
153 rc = phy_read(phydev, MII_KSZPHY_INTCS); in kszphy_ack_interrupt()
170 temp = phy_read(phydev, MII_KSZPHY_CTRL); in kszphy_config_intr()
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); in kszphy_rmii_clk_sel()
216 temp = phy_read(phydev, reg); in kszphy_setup_led()
239 ret = phy_read(phydev, MII_KSZPHY_OMSO); in kszphy_broadcast_disable()
255 ret = phy_read(phydev, MII_KSZPHY_OMSO); in kszphy_nand_tree_disable()
359 ret = phy_read(phydev, MII_BMSR); in ksz8051_ksz8795_match_phy_device()
755 result = phy_read(phydev, MII_CTRL1000); in ksz9031_config_init()
942 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); in ksz8873mll_read_status()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/85xx/
Dmpc85xx_mds.c70 scr = phy_read(phydev, MV88E1111_SCR); in mpc8568_fixup_125_clock()
85 scr = phy_read(phydev, MV88E1111_SCR); in mpc8568_fixup_125_clock()
106 temp = phy_read(phydev, 30); in mpc8568_mds_phy_fixups()
122 temp = phy_read(phydev, 30); in mpc8568_mds_phy_fixups()
127 temp = phy_read(phydev, 30); in mpc8568_mds_phy_fixups()
140 temp = phy_read(phydev, 16); in mpc8568_mds_phy_fixups()
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmach-imx6q.c101 val = phy_read(dev, 0xe); in ar8031_phy_fixup()
108 val = phy_read(dev, 0x1e); in ar8031_phy_fixup()
128 val = phy_read(dev, 0xe); in ar8035_phy_fixup()
141 val = phy_read(dev, 0x0); in ar8035_phy_fixup()

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