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Searched refs:pll0 (Results 1 – 25 of 31) sorted by relevance

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/kernel/linux/linux-5.10/drivers/bcma/
Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
374 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt159 pll0: pll0@800 {
164 clock-output-names = "pll0", "pll0-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
/kernel/linux/linux-5.10/drivers/soc/kendryte/
Dk210-sysctl.c136 u32 clksel0, pll0; in k210_sysctl_clk_recalc_rate() local
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0); in k210_sysctl_clk_recalc_rate()
152 clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0); in k210_sysctl_clk_recalc_rate()
153 clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0); in k210_sysctl_clk_recalc_rate()
154 clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0); in k210_sysctl_clk_recalc_rate()
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dabilis_tb10x.dtsi48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
Dabilis_tb100.dtsi17 pll0: oscillator { label
Dabilis_tb101.dtsi17 pll0: oscillator { label
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstih407-clock.dtsi77 compatible = "st,clkgen-pll0";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
Dstih410-clock.dtsi77 compatible = "st,clkgen-pll0";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
Dstih418-clock.dtsi78 compatible = "st,clkgen-pll0";
115 clk_s_c0_pll0: clk-s-c0-pll0 {
117 compatible = "st,clkgen-pll0";
121 clock-output-names = "clk-s-c0-pll0-odf-0";
Ddove-cubox.dts101 /* connect xtal input as source of pll0 and pll1 */
Dda850.dtsi135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Dhdmi.c36 u32 pll0; member
129 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
144 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
162 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
176 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
190 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
208 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
226 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
245 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
264 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
Dsor.c365 unsigned int pll0; member
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt12 "st,clkgen-pll0"
Dst,clkgen.txt51 compatible = "st,clkgen-pll0";
/kernel/linux/linux-5.10/drivers/clk/mxs/
Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Dda850.c650 void __iomem *pll0; in da850_init_time() local
657 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); in da850_init_time()
660 da850_pll0_init(NULL, pll0, cfgchip); in da850_init_time()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
Dintel_dpll_mgr.c1859 temp |= pll->state.hw_state.pll0; in bxt_ddi_pll_enable()
1993 hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
1994 hw_state->pll0 &= PORT_PLL_M2_MASK; in bxt_ddi_pll_get_hw_state()
2162 dpll_hw_state->pll0 = clk_div->m2_int; in bxt_ddi_set_dpll_hw_state()
2214 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; in bxt_ddi_pll_get_freq()
2272 hw_state->pll0, in bxt_dump_hw_state()
/kernel/linux/linux-5.10/drivers/phy/ti/
DKconfig49 three clock selects (pll0, pll1, dig) and resets for each of the
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dgcc-mdm9615.c40 static struct clk_pll pll0 = { variable
1589 [PLL0] = &pll0.clkr,
Dgcc-ipq806x.c28 static struct clk_pll pll0 = { variable
2756 [PLL0] = &pll0.clkr,
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi401 wiz0_pll0_refclk: pll0-refclk {
458 wiz1_pll0_refclk: pll0-refclk {
515 wiz2_pll0_refclk: pll0-refclk {
572 wiz3_pll0_refclk: pll0-refclk {

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