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Searched refs:ppll (Results 1 – 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_atombios.c569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
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Datombios_crtc.c837 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
840 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
845 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
Damdgpu.h354 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; member
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx35.c65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
110 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
/kernel/linux/linux-5.10/drivers/clk/rockchip/
Dclk-rk3399.c23 ppll, enumerator
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch1984 +PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "dummy_cpll", "gpll", "ppll" };
1988 + "ppll" };
1993 +PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "dummy_cpll", "gpll",
1998 + "ppll", "upll", "xin24m" };
2036 "ppll", "upll", "xin24m" };
2111 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
2112 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
2148 - [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
2149 + [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, CLK_IS_CRITICAL, RK3399_PMU_PLL_CON(0),
2936 - GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
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