Searched refs:psr_context (Results 1 – 8 of 8) sorted by relevance
166 struct psr_context *psr_context) in dce_dmcu_setup_psr() argument178 psr_context->psrExitLinkTrainingRequired); in dce_dmcu_setup_psr()188 switch (psr_context->controllerId) { in dce_dmcu_setup_psr()226 psr_context->sdpTransmitLineNumDeadline); in dce_dmcu_setup_psr()235 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; in dce_dmcu_setup_psr()236 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; in dce_dmcu_setup_psr()238 psr_context->rfb_update_auto_en; in dce_dmcu_setup_psr()239 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; in dce_dmcu_setup_psr()240 masterCmdData1.bits.dcp_sel = psr_context->controllerId; in dce_dmcu_setup_psr()241 masterCmdData1.bits.phy_type = psr_context->phyType; in dce_dmcu_setup_psr()[all …]
195 struct psr_context *psr_context) in dmub_psr_copy_settings() argument223 psr_context->psrExitLinkTrainingRequired); in dmub_psr_copy_settings()227 psr_context->sdpTransmitLineNumDeadline); in dmub_psr_copy_settings()234 copy_settings_data->dpphy_inst = psr_context->transmitterId; in dmub_psr_copy_settings()235 copy_settings_data->aux_inst = psr_context->channel; in dmub_psr_copy_settings()236 copy_settings_data->digfe_inst = psr_context->engineId; in dmub_psr_copy_settings()237 copy_settings_data->digbe_inst = psr_context->transmitterId; in dmub_psr_copy_settings()255 copy_settings_data->psr_level = psr_context->psr_level.u32all; in dmub_psr_copy_settings()256 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; in dmub_psr_copy_settings()257 copy_settings_data->frame_delay = psr_context->frame_delay; in dmub_psr_copy_settings()[all …]
38 …(*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context);
68 struct psr_context *psr_context);
2656 struct psr_context *psr_context) in dc_link_setup_psr() argument2665 psr_context->controllerId = CONTROLLER_ID_UNDEFINED; in dc_link_setup_psr()2706 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; in dc_link_setup_psr()2707 psr_context->transmitterId = link->link_enc->transmitter; in dc_link_setup_psr()2708 psr_context->engineId = link->link_enc->preferred_engine; in dc_link_setup_psr()2716 psr_context->controllerId = in dc_link_setup_psr()2724 psr_context->phyType = PHY_TYPE_UNIPHY; in dc_link_setup_psr()2726 psr_context->smuPhyId = in dc_link_setup_psr()2729 psr_context->crtcTimingVerticalTotal = stream->timing.v_total; in dc_link_setup_psr()2730 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream-> in dc_link_setup_psr()[all …]
228 struct psr_context *psr_context);
724 struct psr_context { struct
9229 struct psr_context psr_context = {0}; in amdgpu_dm_link_setup_psr() local9246 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); in amdgpu_dm_link_setup_psr()