| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/ |
| D | i915_gem_tiling.c | 54 u32 size, unsigned int tiling, unsigned int stride) in i915_gem_fence_size() argument
60 if (tiling == I915_TILING_NONE) in i915_gem_fence_size()
66 stride *= i915_gem_tile_height(tiling); in i915_gem_fence_size()
94 unsigned int tiling, unsigned int stride) in i915_gem_fence_alignment() argument
102 if (tiling == I915_TILING_NONE) in i915_gem_fence_alignment()
112 return i915_gem_fence_size(i915, size, tiling, stride); in i915_gem_fence_alignment()
118 unsigned int tiling, unsigned int stride) in i915_tiling_ok() argument
124 if (tiling == I915_TILING_NONE) in i915_tiling_ok()
127 if (tiling > I915_TILING_LAST) in i915_tiling_ok()
148 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) in i915_tiling_ok()
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| D | i915_gem_object.h | 255 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
257 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
258 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
275 unsigned int tiling, unsigned int stride);
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | fb.c | 43 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
49 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
50 tiling->value = 0; in tegra_fb_get_tiling()
54 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
55 tiling->value = 0; in tegra_fb_get_tiling()
59 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
60 tiling->value = 0; in tegra_fb_get_tiling()
64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
65 tiling->value = 1; in tegra_fb_get_tiling()
69 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
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| D | hub.c | 343 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
357 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_shared_plane_atomic_check()
361 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
512 unsigned long height = state->tiling.value; in tegra_shared_plane_atomic_update()
515 switch (state->tiling.mode) { in tegra_shared_plane_atomic_update()
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| D | plane.h | 45 struct tegra_bo_tiling tiling; member
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| D | gem.h | 43 struct tegra_bo_tiling tiling; member
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| D | dc.c | 417 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
419 switch (window->tiling.mode) { in tegra_dc_setup_window()
436 switch (window->tiling.mode) { in tegra_dc_setup_window()
614 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
641 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_plane_atomic_check()
645 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
737 window.tiling = state->tiling; in tegra_plane_atomic_update()
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| D | plane.c | 61 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
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| D | drm.h | 170 struct tegra_bo_tiling *tiling);
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| D | drm.c | 636 bo->tiling.mode = mode; in tegra_gem_set_tiling()
637 bo->tiling.value = value; in tegra_gem_set_tiling()
658 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
671 args->value = bo->tiling.value; in tegra_gem_get_tiling()
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| D | dc.h | 142 struct tegra_bo_tiling tiling; member
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| D | gem.c | 351 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_mman.c | 24 unsigned int tiling; member
37 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
43 if (tile->tiling == I915_TILING_X) { in tiled_offset()
96 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mapping()
99 tile->tiling, tile->stride, err); in check_partial_mapping()
103 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); in check_partial_mapping()
154 tile->tiling ? tile_row_pages(obj) : 0, in check_partial_mapping()
155 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride, in check_partial_mapping()
181 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mappings()
184 tile->tiling, tile->stride, err); in check_partial_mappings()
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| D | i915_gem_client_blt.c | 139 u32 tiling; member
169 if (src->tiling == I915_TILING_Y) in prepare_blit()
171 if (dst->tiling == I915_TILING_Y) in prepare_blit()
188 if (src->tiling) { in prepare_blit()
194 if (dst->tiling) { in prepare_blit()
287 t->buffers[i].tiling = in tiled_blits_create_buffers()
313 unsigned int tiling) in tiled_offset() argument
318 if (tiling == I915_TILING_NONE) in tiled_offset()
323 if (tiling == I915_TILING_X) { in tiled_offset()
360 static const char *repr_tiling(int tiling) in repr_tiling() argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_ggtt_fencing.c | 89 if (fence->tiling) { in i965_write_fence_reg()
98 if (fence->tiling == I915_TILING_Y) in i965_write_fence_reg()
130 if (fence->tiling) { in i915_write_fence_reg()
132 unsigned int tiling = fence->tiling; in i915_write_fence_reg() local
133 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
164 if (fence->tiling) { in i830_write_fence_reg()
168 if (fence->tiling == I915_TILING_Y) in i830_write_fence_reg()
221 fence->tiling = 0; in fence_update()
239 fence->tiling = i915_gem_object_get_tiling(vma->obj); in fence_update()
315 fence->tiling = 0; in i915_vma_revoke_fence()
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| D | intel_ggtt_fencing.h | 59 u32 tiling; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_render_cl.c | 440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
491 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
568 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
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| D | vc4_plane.c | 638 u32 tiling, src_y; in vc4_plane_mode_set() local
676 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
739 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
772 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
776 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
780 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
835 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
885 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
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| /kernel/linux/linux-5.10/drivers/staging/media/ipu3/ |
| D | ipu3-css-params.c | 313 unsigned int tiling; member
426 unsigned int tiling = 0; in imgu_css_osys_calc_frame_and_stripe_params() local
466 &tiling); in imgu_css_osys_calc_frame_and_stripe_params()
472 frame_params[pin].tiling = tiling; in imgu_css_osys_calc_frame_and_stripe_params()
1001 fr_pr->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
1084 if (frame_params[pin].tiling) { in imgu_css_osys_calc()
1153 param->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
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| D | ipu3-abi.h | 919 u32 tiling; member
1025 u32 tiling; /* enum imgu_abi_osys_tiling */ member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 343 unsigned int tiling, in get_meta_and_pte_attr() argument
348 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
419 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
457 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| D | display_rq_dlg_calc_20.c | 343 unsigned int tiling, in get_meta_and_pte_attr() argument
348 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
419 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
457 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 330 unsigned int tiling, in get_meta_and_pte_attr() argument
336 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
411 (enum dm_swizzle_mode) (tiling), in get_meta_and_pte_attr()
449 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 377 unsigned int tiling, in get_meta_and_pte_attr() argument
384 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
454 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
494 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 389 int tiling, in dml1_rq_dlg_get_row_heights() argument
394 bool surf_linear = (tiling == dm_sw_linear); in dml1_rq_dlg_get_row_heights()
445 if (tiling != dm_sw_linear) in dml1_rq_dlg_get_row_heights()
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