Searched refs:vdsc_cfg (Results 1 – 6 of 6) sorted by relevance
256 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) in drm_dsc_compute_rc_parameters() argument266 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()268 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, in drm_dsc_compute_rc_parameters()272 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()273 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()277 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, in drm_dsc_compute_rc_parameters()281 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()282 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()286 if (vdsc_cfg->convert_rgb) in drm_dsc_compute_rc_parameters()287 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + in drm_dsc_compute_rc_parameters()[all …]
383 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params() local388 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()389 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; in intel_dsc_compute_params()390 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()394 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()396 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()399 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params()400 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()408 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; in intel_dsc_compute_params()416 vdsc_cfg->rc_buf_thresh[12] = 0x7C; in intel_dsc_compute_params()[all …]
1479 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local1495 vdsc_cfg->convert_rgb = true; in gen11_dsi_dsc_compute_config()1502 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()1503 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()1505 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()1506 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()1508 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()1510 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); in gen11_dsi_dsc_compute_config()
2486 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local2489 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()2490 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()2544 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()2546 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()2548 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
2181 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params() local2194 if (vdsc_cfg->pic_height % 8 == 0) in intel_dp_dsc_compute_params()2195 vdsc_cfg->slice_height = 8; in intel_dp_dsc_compute_params()2196 else if (vdsc_cfg->pic_height % 4 == 0) in intel_dp_dsc_compute_params()2197 vdsc_cfg->slice_height = 4; in intel_dp_dsc_compute_params()2199 vdsc_cfg->slice_height = 2; in intel_dp_dsc_compute_params()2201 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()2204 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()2209 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()2219 if (vdsc_cfg->dsc_version_minor == 2) in intel_dp_dsc_compute_params()[all …]
607 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);