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Searched refs:ADDR_SW_64KB_R_X (Results 1 – 10 of 10) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/src/gfx10/
Dgfx10addrlib.h95 (1u << ADDR_SW_64KB_R_X);
117 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
125 (1u << ADDR_SW_64KB_R_X) |
152 (1u << ADDR_SW_64KB_R_X) |
160 (1u << ADDR_SW_64KB_R_X);
179 (1u << ADDR_SW_64KB_R_X);
192 (1u << ADDR_SW_64KB_R_X);
Dgfx10addrlib.cpp741 (pIn->swizzleMode != ADDR_SW_64KB_R_X) || in HwlSupportComputeDccAddrFromCoord()
3110 swMode[AddrBlockThin64KB] = ADDR_SW_64KB_R_X; in HwlGetPreferredSurfaceSetting()
3225 … if (GetBlockSizeLog2(swMode[AddrBlockThinVar]) < GetBlockSizeLog2(ADDR_SW_64KB_R_X)) in HwlGetPreferredSurfaceSetting()
4622 ADDR_SW_64KB_R_X, in HwlComputeMaxMetaBaseAlignments()
4623 m_blockVarSizeLog2 ? ADDR_SW_VAR_R_X : ADDR_SW_64KB_R_X, in HwlComputeMaxMetaBaseAlignments()
4653 ADDR_SW_64KB_R_X, in HwlComputeMaxMetaBaseAlignments()
4654 m_blockVarSizeLog2 ? ADDR_SW_VAR_R_X : ADDR_SW_64KB_R_X, in HwlComputeMaxMetaBaseAlignments()
/third_party/mesa3d/src/amd/addrlib/src/gfx11/
Dgfx11addrlib.h88 (1u << ADDR_SW_64KB_R_X);
113 const UINT_32 Gfx11RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
121 (1u << ADDR_SW_64KB_R_X) |
131 (1u << ADDR_SW_64KB_R_X) |
153 (1u << ADDR_SW_64KB_R_X);
175 (1u << ADDR_SW_64KB_R_X) |
Dgfx11addrlib.cpp391 const UINT_8* patIdxTable = (pIn->swizzleMode == ADDR_SW_64KB_R_X) ? in HwlComputeDccInfo()
526 ((pIn->swizzleMode != ADDR_SW_64KB_R_X) && in HwlSupportComputeDccAddrFromCoord()
565 const UINT_8* patIdxTable = (pIn->swizzleMode == ADDR_SW_64KB_R_X) ? in HwlComputeDccAddrFromCoord()
2615 swMode[AddrBlockThin64KB] = ADDR_SW_64KB_R_X; in HwlGetPreferredSurfaceSetting()
3600 … ADDR_ASSERT((swizzleMode == ADDR_SW_64KB_Z_X) || (swizzleMode == ADDR_SW_64KB_R_X)); in GetSwizzlePatternInfo()
4036 ADDR_SW_64KB_R_X, in HwlComputeMaxMetaBaseAlignments()
4066 ADDR_SW_64KB_R_X, in HwlComputeMaxMetaBaseAlignments()
/third_party/mesa3d/src/amd/addrlib/src/gfx9/
Dgfx9addrlib.h115 (1u << ADDR_SW_64KB_R_X);
142 (1u << ADDR_SW_64KB_R_X);
151 (1u << ADDR_SW_64KB_R_X);
199 (1u << ADDR_SW_64KB_R_X);
/third_party/mesa3d/src/amd/addrlib/inc/
Daddrtypes.h271 ADDR_SW_64KB_R_X = 27, enumerator
/third_party/mesa3d/src/amd/common/
Dac_surface_meta_address_test.c330 swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_R_X; in run_dcc_address_test()
333 swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_R_X; in run_dcc_address_test()
Dac_surface.c1513 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X || in is_dcc_supported_by_CB()
1517 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X; in is_dcc_supported_by_CB()
2460 case ADDR_SW_64KB_R_X: in gfx9_compute_surface()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_test_image_copy_region.c444 [ADDR_SW_64KB_R_X] = "64KB_R_X", in print_image_attrs()
Dsi_texture.c303 surface->u.gfx9.swizzle_mode = ADDR_SW_64KB_R_X; in si_init_surface()